VHDL 将多个 std_logic_vector 输出分组为单个 std_logic_vector
我必须通过聚合我已经设计的 8 个 4 位 ALU 来设计一个 32 位 ALU。我不明白的是如何获取 8 个 4 位信号并将它们链接到 32 位 ALU 的 32 位信号。
我想说这样的话（对于最低的 4 位 ALU）：
a0: four_bit_ALU port map(A => A(3 downto 0),
B => B(3 downto 0),
Cin => sub,
Less => l,
Cout => c(0),
Result => result(3 downto 0),
OP => m);
其中“A”和“B”是 ALU 的两个参数，“结果”是 32 位输出。测试此结果会给出所有未定义的结果位。我测试过4位ALU，没有出现这样的问题。
I have to design a 32-bit ALU by aggregating 8 4-bit ALU's I've already designed. What I can't figure out is how to take the 8 4-bit signals and link them to the 32-bit signals for the 32-bit ALU.
I want to say something like this (for the lowest 4-bit ALU):
a0: four_bit_ALU port map(A => A(3 downto 0),
B => B(3 downto 0),
Cin => sub,
Less => l,
Cout => c(0),
Result => result(3 downto 0),
OP => m);
Where 'A' and 'B' are the two arguments to the ALU and 'result' is the 32-bit output. Testing this gives all the result bits as undefined though. I have tested the 4-bit ALU and have no such problems.
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猜测：您是否可能在 4 位 ALU 的输入上犯了错误，并留下了诸如 Cin 之类的东西与未定义的信号相关联？
如果您期望除了受过少量教育的猜测之外的任何帮助，您将不得不发布更多代码。
Guess: Did you perhaps make a goof on the inputs to your 4-bit ALU, and leave something like Cin tied to an undefined signal?
You'll have to post more code if you expect any help other than slightly educated guesses.