.c 文件旁边带有 .s 文件的 makefile

发布于 2024-10-31 04:04:17 字数 1904 浏览 0 评论 0原文

我有一个裸机项目,其中包括 .c 文件旁边的 .s 文件。如何编写 makefile 将 .s 文件的编译与 .c 文件分开?这些文件位于程序的子文件夹(源、包含、启动)中。

我正打算做这样的事情。这好吗?那么如何将对象链接到可执行文件中呢?

SHELL := /bin/bash
ROOT := $(shell pwd)
VPATH := $(ROOT)/source:/$(ROOT)/startup:$(ROOT)/include
EXE := exe
OBJECTS_GCC := $(patsubst %.c,%.o,$(wildcard *.c))
OBJECTS_AS := $(patsubst %.s,%.o,$(wildcard *.s))
AS := arm-none-eabi-as -mcpu=arm926ej-s -Wall
GCC := arm-none-eabi-gcc -mcpu=arm926ej-s -Wall
LD := arm-none-eabi-ld -T test.ld -o $(EXE)

all: $(EXE)
$(EXE): startups sources

startups: $(OBJECTS_AS)
    $(AS) $(OBJECTS_AS)

sources: $(OBJECTS_GCC)
    $(GCC) $(OBJECTS_GCC)

我很难找到任何包含 .s 文件和 .c 文件的示例。

问候。


这是最新版本的 makefile,其中没有找到 header.h:

SHELL := /bin/bash
ROOT := $(shell pwd)
INC := $(ROOT)/inc
SRC := $(ROOT)/src
STR := $(ROOT)/str
EXE := exe
AS := arm-none-eabi-as -mcpu=arm926ej-s -c -Wall -I $(INC) -I$(SRC) -I $(STR)
GCC := arm-none-eabi-gcc -mcpu=arm926ej-s -c -Wall -I $(INC) -I$(SRC) -I $(STR)
LDSCRIPT := test.ld
LD := arm-none-eabi-ld -T $(LDSCRIPT)
HEADERS := $(notdir $(wildcard $(INC)/*.h))
SOURCES_GCC := $(notdir $(wildcard $(SRC)/*.c))
SOURCES_AS := $(notdir $(wildcard $(STR)/*.s))
OBJECTS_GCC := $(SOURCES_GCC:.c=.o)
OBJECTS_AS := $(SOURCES_AS:.s=.o)
VPATH := $(STR):$(SRC):$(INC)

all : $(EXE)
    @echo konec postopka: izvrsljiv program po imenu $(EXE) se nahaja v mapi $(ROOT)

$(EXE) : $(OBJECTS_AS) $(OBJECTS_GCC)
    @echo objekti so: $(OBJECTS_AS) $(OBJECTS_GCC)
    @echo headerji so: $(HEADERS)
    @echo linkanje objektov v izvrsljiv program...
    $(LD) -o $@ $^

%.o : %.s %.h
    @echo prevajanje ASSEMBLY izvornih datotek...
    $(AS) -o $@  $<

%.o : %.c %.h
    @echo prevajanje C izvornih datotek...
    $(GCC) -o $@ $<

.PHONY : clean
clean :
    @echo brisanje objektov
    rm *.o
    @echo brisanje izvrsljivega programa
    rm $(EXE)

I have a baremetal project which includes .s files beside .c files. How can I write a makefile where I separate the compilation of the .s files from the .c files? The files are located in subfolders (source, include, startup) of a program.

I was going for something like this. Is this good? How can I link the objects into an executable then?

SHELL := /bin/bash
ROOT := $(shell pwd)
VPATH := $(ROOT)/source:/$(ROOT)/startup:$(ROOT)/include
EXE := exe
OBJECTS_GCC := $(patsubst %.c,%.o,$(wildcard *.c))
OBJECTS_AS := $(patsubst %.s,%.o,$(wildcard *.s))
AS := arm-none-eabi-as -mcpu=arm926ej-s -Wall
GCC := arm-none-eabi-gcc -mcpu=arm926ej-s -Wall
LD := arm-none-eabi-ld -T test.ld -o $(EXE)

all: $(EXE)
$(EXE): startups sources

startups: $(OBJECTS_AS)
    $(AS) $(OBJECTS_AS)

sources: $(OBJECTS_GCC)
    $(GCC) $(OBJECTS_GCC)

I am having a hard time finding any example at all which includes .s files alongside .c files.

Regards.


Here is the latest version of makefile, where header.h isn't found:

SHELL := /bin/bash
ROOT := $(shell pwd)
INC := $(ROOT)/inc
SRC := $(ROOT)/src
STR := $(ROOT)/str
EXE := exe
AS := arm-none-eabi-as -mcpu=arm926ej-s -c -Wall -I $(INC) -I$(SRC) -I $(STR)
GCC := arm-none-eabi-gcc -mcpu=arm926ej-s -c -Wall -I $(INC) -I$(SRC) -I $(STR)
LDSCRIPT := test.ld
LD := arm-none-eabi-ld -T $(LDSCRIPT)
HEADERS := $(notdir $(wildcard $(INC)/*.h))
SOURCES_GCC := $(notdir $(wildcard $(SRC)/*.c))
SOURCES_AS := $(notdir $(wildcard $(STR)/*.s))
OBJECTS_GCC := $(SOURCES_GCC:.c=.o)
OBJECTS_AS := $(SOURCES_AS:.s=.o)
VPATH := $(STR):$(SRC):$(INC)

all : $(EXE)
    @echo konec postopka: izvrsljiv program po imenu $(EXE) se nahaja v mapi $(ROOT)

$(EXE) : $(OBJECTS_AS) $(OBJECTS_GCC)
    @echo objekti so: $(OBJECTS_AS) $(OBJECTS_GCC)
    @echo headerji so: $(HEADERS)
    @echo linkanje objektov v izvrsljiv program...
    $(LD) -o $@ $^

%.o : %.s %.h
    @echo prevajanje ASSEMBLY izvornih datotek...
    $(AS) -o $@  
lt;

%.o : %.c %.h
    @echo prevajanje C izvornih datotek...
    $(GCC) -o $@ 
lt;

.PHONY : clean
clean :
    @echo brisanje objektov
    rm *.o
    @echo brisanje izvrsljivega programa
    rm $(EXE)

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一指流沙 2024-11-07 04:04:17

考虑一下在没有 make 的情况下您会发出哪些命令。你会采取什么步骤?您首先创建哪些文件,文件在创建之前如何依赖于其他文件的存在?
一旦您对此有了清晰的认识,就可以编写模仿这些命令的 make 规则,但要包含 make 变量。

如果您掌握了这些,您就可以通过使用隐式规则、自动变量等来增强您的 makefile,但首先要保持简单,直到您掌握 make 的工作原理。

有几点:

  • 我认为通配符函数不会以这种方式获取任何文件名。它只在当前目录中查找,不使用VPATH 在其他目录中查找。
  • 您可以使用 gcc 将对象作为输入。这样它将(尝试)创建一个可执行文件。
  • 您没有创建目标文件的规则。如果您依赖 make 的内置隐式规则或模式规则,这可能没问题,但它不会使用您想要使用的 gcc 版本及其关联标志。您必须设置一些其他变量才能使其正常工作(例如 CCCFLAGS 等)。
  • 您已经定义了LD,但从未使用过它。在配方中使用它来创建可执行文件。

我想你应该有更多类似这样的东西:

all: $(EXE)

$(EXE): $(OBJECTS_AS) $(OBJECTS_GCC)
    $(LD) $^

%.o: %.s
    $(AS) 
lt;

%.o: %.c
    $(GCC) -c 
lt;

Think about what commands you would issue without make. What steps would you take? Which files do you create first, and how do files depend on the existence of others before they can be made?
Once you have a clear picture of that, write make rules that mimic those commands, but with the inclusion of make variables.

If you have that down, you can then enhance your makefile by using things like implicit rules, automatic variables, and such, but keep it simple at first, until you get a grasp of how make works.

A couple of points:

  • I don't think the wildcard function will pick up any file names in this way. It only looks in the current directory, and doesn't use VPATH to search in others.
  • You use gcc with the objects as inputs. This way it will (try to) create an executable.
  • You have no rules to create the object files. This may be fine if you rely on make's built-in implicit or pattern rules, but it won't use the version of gcc you want to use, with it's associated flags. You have to set up some other variables for that to work (like CC, CFLAGS, and such).
  • You have defined LD, but never use it. Use it in a recipe to create the executable.

I guess you should have something more like this:

all: $(EXE)

$(EXE): $(OBJECTS_AS) $(OBJECTS_GCC)
    $(LD) $^

%.o: %.s
    $(AS) 
lt;

%.o: %.c
    $(GCC) -c 
lt;
~没有更多了~
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