内存排序和正确编程实践的保证
关于我在下面描述的顺序，我有一些相关的问题。
考虑到这些排序保证，我在很多地方都不需要明确的围栏。但是，我如何向编译器（特别是 GCC）表达“栅栏”？也就是说，程序顺序的保证仅适用于优化器不重新排序我的程序的情况。
是否有正在使用的常见/流行的新芯片具有不提供此类保证的通用内核？
我对 C++0x 的交错概念有点困惑。我必须使用“原子”类来利用这些保证，还是草案中是否有其他方面也提供了利用这些保证的方法？
内存排序
Intel 和 AMD（至少对于 x86_64）都保证内存加载相对于在单个处理器上完成的存储操作是连续的。也就是说，如果某个处理器执行这些存储：
- Store A <- 1
- Store B <- 2
- Store C <- 3
当某个其他处理器看到 C(3) 时，它保证也看到先前的存储 A(1 ) 和 B(2)。现在，处理器之间的可见性可能是交错的，但来自任何给定处理器的存储顺序也将是连续的。
当处理器 0 读取处理器 1 存储的值，然后写入一个值时，它们还具有传递保证，读取新值的处理器 2 也必须看到来自处理器 1 的该值。
忽略处理 IO 和特殊设备的特殊情况。我只对一般内存保证感兴趣：我在这里的排序只是我最感兴趣的一点，因为它对并发算法最重要。
With respect to the ordering I describe below I have some related questions.
Given these ordering guarantees I don't need explicit fences in many places. However, how can I express the "fence" to the compiler, in particular GCC? That is, the guarantee of program order only applies so long as the optimizer doesn't reorder my program.
Are there common/popular new chips in use that have general purpose cores that do not offer such guarantees?
I'm a bit confused in C++0x with its idea of interleaving. Must I use the "atomic" class to make use of these guarantees, or is there some other aspect in the draft which also provides a way to make use of these guarantees?
Memory Ordering
Both Intel and AMD, at least with x86_64, guarantee that memory loads are sequential with respect to the store operations done on a single processor. That is, if some processor executes these stores:
- Store A <- 1
- Store B <- 2
- Store C <- 3
The moment some other processor sees C(3) it is guaranteed to also see the previous stores A(1) and B(2). Now, the visibility between processors may be interleaved, but the store order from any given processor will also be sequential.
They also have transitive guarantees when Processor 0 reads a value stored by Processor 1, then writes a value, that Processor 2 reading the new value must also see that value from Processor 1.
Ignore the special cases dealing with IO and special devices. I'm interested only in the general memory guarantees: my ordering here is just the bit I'm most interested in as it has the most significance for concurrent algorithms.
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为了最有力地保证您的存储和加载将按精确所需的顺序执行，您可能需要在代码中使用
asm块并写出您的mov明确指示。For the strongest guarantees that your stores and loads will be executed in precisely the required order, you may need to resort to
asmblocks in your code and write out yourmovinstructions explicitly.即使平台保证顺序一致性，当多个线程访问同一内存位置并且至少访问其中一个内存位置时，您总是需要某种同步来防止竞争条件写入其中。 C++0x 提供了三种方法来实现此类同步：
std::mutex和相关类std::atomicstd::atomic_thread_fence。后两者接受内存顺序参数，在不保证顺序一致性的平台上允许额外的灵活性（仅适用于专家！），但这与 x86 无关。
Even if the platform guarantees sequential consistency, you will always need some sort of synchronization to prevent race conditions when more than one thread accesses the same memory location and at least one of them writes into it. C++0x offers three ways to implement such synchronization:
std::mutexand related classesstd::atomic<T>std::atomic_thread_fence.The latter two accept a memory order parameter permitting extra flexibility (for experts only!) on platforms that do not guarantee sequential consistency, but this is not relevant on x86.
掌握这些类型的操作对于构建 SMP 操作系统以及与某些类型的硬件进行通信至关重要。 Linux 内核文档提供了对该主题的精彩概述以及内核使用的特定解决方案。我强烈建议您查看他们的 memory-barriers.txt 文件。
Mastery of these kinds of operations is essential for building SMP operating systems and for communicating with certain kinds of hardware. The Linux kernel documentation provides an excellent overview of the subject along with the specific solutions used by the kernel. I highly recommend taking a look at their memory-barriers.txt file.