系统 verilog 中没有类型的输入

发布于 2024-10-29 07:01:14 字数 306 浏览 7 评论 0原文

我在一个模块的输入和输出的系统verilog代码解码示例中遇到过，没有说明它们的类型，例如logic、wire ...

module mat_to_stream (
  input [2:0] [2:0] [2:0] a,b,
  input newdata,
  input rst, clk,
  output [2:0] [7:0] A_out, B_out);
  ...rest of code...

声明逻辑和不声明任何类型之间有什么区别？

原文

I've encountered in an example for a system verilog code decleration of inputs and outputs for a module without stating their type, e.g logic, wire...

module mat_to_stream (
  input [2:0] [2:0] [2:0] a,b,
  input newdata,
  input rst, clk,
  output [2:0] [7:0] A_out, B_out);
  ...rest of code...

What is the diffrence between stating logic and not stating any type?

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战皆罪 2024-11-05 07:01:14

声明逻辑和不声明任何类型之间没有区别。

input newdata,

相当于

input logic newdata,

SystemVerilog IEEE Std (1800-2009) 在“23.2.2.3 确定端口类型、数据类型和方向的规则”部分对此进行了描述。

There is no difference between stating logic and not stating any type.

input newdata,

is equivalent to

input logic newdata,

The SystemVerilog IEEE Std (1800-2009) describes this in section: "23.2.2.3 Rules for determining port kind, data type and direction".

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垂暮老矣 2024-11-05 07:01:14

不为输入分配数据类型是很常见的，因为它们几乎总是wire。

input [7:0] newdata

名义上相当于：

input wire [7:0] newdata

它实际上是在拾取 `default_nettypewire ，可以将其更改为 uwire 以强制编译器检查唯一的驱动程序，这将因多个接线错误而失败驱动器。

使用logic作为类型可以在wire和reg之间进行自动选择，这对于输出很有用，并且可以更容易地折射。输入永远不能是 reg 类型。

Stuart Sutherlands SNUG2013 论文，第 12 节介绍了uwire 可用于更好地暗示设计意图。

It is very common to not assign inputs a data type, as they should almost always be wire.

input [7:0] newdata

Is nominally equivalent to:

input wire [7:0] newdata

It is actually picking up `default_nettype wire which could be changed to say uwire to enforce compiler checks for unique drivers, which will fail on wiring mistakes with multiple drives.

Using logic as a type allows the auto selection between wire and reg which is useful for outputs and allows easier refracting. Inputs can never be reg type.

Stuart Sutherlands SNUG2013 paper, section 12 covers how uwire could be used to better imply design intent if it was supported correctly by the tools.

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