调试 VHDL：如何？
我是 VHDL 的新手，不知道如何调试 VHDL 代码。
有没有任何软件可以让我随着时间的推移了解 VHDL 实体的内部信号或类似的东西？
请帮忙。
I am a newbie to VHDL and can't figure out how to debug VHDL code.
Is there any software that could probably give me an insight to the internal signals of my VHDL entity as time passes or something like that?
Please help.
如果你对这篇内容有疑问，欢迎到本站社区发帖提问 参与讨论，获取更多帮助，或者扫码二维码加入 Web 技术交流群。
绑定邮箱获取回复消息
由于您还没有绑定你的真实邮箱，如果其他用户或者作者回复了您的评论，将不能在第一时间通知您！
发布评论
评论（8）
正如其他帖子所指出的，您可能需要一个 模拟器，例如 GHDL。但是，要调试您的模拟，有几种不同的方法：
经典打印语句 - 只需在
writeline(output,[...])中混合即可你的程序代码。 查看这个 hello world 示例。 如果您只是开始，然后添加打印语句将是非常有价值的。对于我所做的大多数模拟调试（这是我工作的一部分），我几乎所有调试都是基于我们在设计中建立的打印语句和 测试平台。只是为了最终的调试，或者对于更困难的问题，我使用下一个调试方法。“转储”模拟（对于 GHDL，请参阅此页面 和这个 ）。这是您的设计（或设计的子集）的逐周期跟踪。这就好像您将逻辑分析仪连接到设计中的每条线路。您可能想要的有关设计的所有信息，但级别非常低——信号级别。要使用此方法：
创建模拟“转储”。此类转储的基本格式是值更改转储或VCD。无论您使用哪种模拟器，您都需要阅读有关如何创建 VCD 的文档。 （您还可以在文档中搜索“dump”——您的模拟器可能使用不同的文件格式进行转储。）
创建模拟转储后，即可将转储加载到波形查看器< /a>.如果您使用 gEDA 包，那么您将使用 gtkwave 查看转储。
注意如果您想使用 GHDL 和 gtkwave 来调试 VHDL 代码，您可以将它们安装在 ubuntu 上 使用命令：（
假设您对运行 ubuntu 的计算机具有 root 访问权限）
As the other posts have pointed out, you'll likely need a simulator like GHDL. However, to debug your simulation, there are a few different methodologies:
Classic print statements -- just mix in
writeline(output,[...])in your procedural code. See this hello world example. If you're just getting started, then adding print statements will be invaluable. For most of the simulation debug that I do ( and that is part of my job ), I do almost all of the debug based on print statements that we've built up in our design and testbench. It is only for the final debug, or for more difficult issues that I use the next debug method."Dumping" the simulation ( for GHDL see this page and this one ). This is a cycle by cycle trace of your design ( or a subset of your design). It's as if you hook up a logic analyzer to every single wire in your design. All the info you could ever want about your design, but at a very low level -- the signal level. To use this methodology:
Create a simulation "dump". The base format for such a dump is a Value Change Dump or VCD. Whichever simulator you use, you'll need to read the documentation on how to create a VCD. ( You can also search "dump" in your docs -- your simulator may use a different file format for its dumps.)
Once you create a simulation dump, you then load your dump into a wave-form viewer. If you're using the gEDA package, then you would use gtkwave to view the dump.
note If you want to use GHDL and gtkwave to debug your VHDL code, you can install them on ubuntu with command:
( assuming you have root access to the machine running ubuntu)
Xilinx 提供其设计套件的免费版本：http://www.xilinx.com/tools/webpack。嗯。 Webpack 包含 VHDL 模拟器，尽管上次尝试时我更喜欢 ModelSim 的模拟器。但它可能已经改变了。
Wepack 也与 ModelSim 不同，因为它不仅是模拟器，而且是成熟的 FPGA 设计套件。
ModelSim 的缺点是它的许可证——就我而言，它只对学生免费。
Xilinx offers free version of its design suite: http://www.xilinx.com/tools/webpack.htm. Webpack contains VHDL simulator, although last time I tried I've liked ModelSim's simulator better. It might have changed though.
Wepack is also different from ModelSim as it's not only simulator but full-fledged FPGA design suite.
ModelSim's disadvantage is its license -- as far as I'm concerned it's free for students only.
根据成本和可用性，这里提到的其他可能更合适。然而，迄今为止我用过的最好的 HDL/网表调试器是 Verdi。
The others mentioned here are likely more appropriate based on cost and availability. However the best HDL/netlist debugger I've used by far is Verdi.
您正在寻找的是 VHDL 模拟器。有多种替代方案可供选择：
Simili 软件作为免费版本提供，但性能有限。
安装模拟器后，您需要学习如何使用它。一般来说，您还必须用 VHDL 编写测试平台，但某些模拟器将允许您从图形用户界面创建刺激信号。您可以在此页面上找到大量基于 VHDL 的测试平台示例：VHDL 教程 。
在模拟器中，您可以在波形查看器中直观地检查设计的状态，还可以在代码中设置断点来调试设计。
What you are looking for is an VHDL simulator. There are several alternatives to choose from:
The Simili software is available as a free version with limited performance.
Once you have the simulator installed you need to learn how to use it. Generally you will have to write a testbench in VHDL too, but some of the simulators will let you create the stimuli signals from a graphical user interface. You can find a large number of examples of VHDL-based testbenches on this page: VHDL Tutorials.
In the simulator you are able to visually inspect the state of your design in the waveform viewer and also be able to set breakpoints in your code to debug the design.
使用
ModelSim等仿真软件。这类软件通常相当昂贵。一般来说，如果使用 vhdl 合成器，您将获得它的一些轻量级变体或类似的软件，这足以处理较小的事情。Use a simulation software like
ModelSim. This kind of software is usually quite expensive. In general if with your vhdl synthethizer you'll get some lightweight variant of it or similar software which is enough for smaller things.对于不完全推动语言规范的小型工作，GHDL 作为模拟器 IME 可以很好地工作。当您进一步推进时（而且您必须这样做，您无法仅在芯片中调试任何相当大的代码段），您可能会发现您需要花一些钱购买 Mentor 的 Modelsim/Questa 或 Aldec 的 ActiveHDL/Riviera 之类的东西。
For small jobs which don't push the language spec all the way, GHDL works fine as a simulator IME. As you push things further (and you must, you can't debug any sizeable piece of code just in silicon) you may find you need to spend some money on something like Mentor's Modelsim/Questa or Aldec's ActiveHDL/Riviera.
首先，我创建了测试台来测试我的组件，使用 isim 来模拟这个测试台，我在主代码区域中插入了断点，使用单步执行按钮单步执行代码，或者使用运行按钮跳转到下一个断点
就像我习惯使用任何编程语言一样
first i created test bench to test my component, used isim to simulate this test bench, i inserted break points in the main code areas, used the step into button to step into code, or the run button to jump to next break point
same as i am used to do with any programming language
“调试”VHDL 的专业方法是创建“测试平台”。与其他 VHDL 一样，它很复杂。这是“如何测试平台”链接：vhdl 测试平台< /a>
我很懒。我也不是专业的。我更喜欢做所谓的“强迫”。如果您使用的是 Xilinx、ModelSim 或 Vivado，那么您就可以将 VHDL 代码放入“模拟”中。您可以在其中将信号添加到波形，选择这些信号（右键单击它们）并强制将它们的值设置为“0”或“1”。然后，在“强制”输入后，运行模拟几纳秒并查看输出。
The professional way to “Debug” VHDL is to create a “testbench”. Like everything else VHDL it’s complicated. Here’s a “how to testbench” link: vhdl Testbenches
I am very lazy. I am also not professional. I prefer to do what is known as “forcing”. If you are using Xilinx, ModelSim, or Vivado, then you have the ability to toss your VHDL code into a “simulation”. There you can add signals to a waveform, select those signals (right click on them) and force their values to be ‘0’ or ‘1’. Then after “forcing” your input, run the simulation for a few nanoseconds and look at the output.