ARM 模式为何有这么多？
我目前正在阅读/学习 ARM 架构...... 我想知道为什么有这么多模式 （FIQ、用户、系统、管理员、IRQ，...）。
我的问题是为什么我们需要这么多模式？仅仅用户和系统还不够吗？
提前致谢。
I'm currently reading/learning about ARM architecture ...
and I was wondering why there are so many modes
(FIQ, User, System, Supervisor, IRQ, ...).
My question is why do we need so many modes? Wouldn't just User and System be enough?
Thanks in advance.
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这只是一个架构决定。多种模式的一大优点是它们有一些存储的寄存器。这些额外的寄存器允许您编写更简单的异常例程。
如果您只选择两个，那么 USR 和 SYS 可能是不错的选择，但是当您例外时会发生什么？正常的ARM模型是进入异常模式，设置该异常模式的banked链接寄存器指向解决异常后要返回的指令，将处理器状态保存在异常模式的SPSR寄存器中，然后跳转到异常向量。 USR 和 SYS 共享它们的所有寄存器 - 使用此模型，每次中断时都会清除函数返回地址（以 LR 表示）！
特别是 FIQ 模式比其他异常模式具有更多的分组寄存器。这些额外的寄存器与 FIQ 的“F”部分一致 - 它代表“快速”。不必在软件中保存和恢复更多处理器上下文将加快您的中断处理程序的速度。
It's just an architectural decision. The big advantage of the multiple modes is that they have some banked registers. Those extra registers allow you to write much less complicated exception routines.
If you were to pick only two, just USR and SYS are probably as good a choice as any, but what would happen when you took an exception? The normal ARM model is to go to an exception mode, set the banked link register for that exception mode to point to the instruction you want to return to after you resolve the exception, save the processor state in the exception mode's SPSR register, and then jump to the exception vector. USR and SYS share all their registers - using this model, you'd blow away your function return address (in LR) every time you took an interrupt!
The FIQ mode in particular has even more banked registers than the other exception modes. Those extra registers are in keeping with the "F" part of FIQ - it stands for "Fast". Not having to save and restore more processor context in software will speed up your interrupt handler.
卡尔的回答没有太多可补充的。不确定您正在谈论的 ARM 处理器的系列/架构，因此我将根据您的问题（FIQ、IRQ 等）假设您正在谈论 ARM7/9/11。我不会列举每个 ARM 架构变体中每个模式之间的所有差异。
除了 Carl 所说的之外，针对不同情况使用不同模式的其他一些优点：
例如，在 FIQ 中，您不必立即分支，您可以继续执行。除了其他例外，您必须立即分支
对于不同的模式，某些寄存器（例如 CPSR、MMU 寄存器等 - 取决于体系结构）是禁止使用的。某些指令也是如此。您不想让用户代码修改特权寄存器，现在是吗？
Not too much to add to Carl's answer. Not sure what family / architecture of ARM processors you're talking about, so I'll just assume based on your question (FIQ, IRQ, etc.) that you're talking about ARM7/9/11. I won't enumerate every difference between every mode in every ARM architecture variant.
In addition to what Carl said, a few other advantages of having different modes for different circumstances:
for example, in the FIQ, you don't have to branch off right away, you can just keep on executing. With other exceptions you have to branch right away
with different modes, you have natural support for separate stacks. If you're multitasking (e.g., RTOS) and you don't have a separate stack when you're in an interrupt mode, you have to build-in extra space onto each task stack for the worst-case interrupt situation
with different modes, certain registers (e.g. CPSR, MMU regs, etc. - depends on architecture) are off-limits. Same thing with certain instructions. You don't want to let user code modify privileged registers, now do you?