了解芯片的频率/振荡
我根本不知道它是什么。 甚至不知道如何去寻找它是什么。 我将非常感谢任何帮助。
I have literally no clue what it is.
Wouldn't even know how to go about finding what it is.
I would greatly appreciate any help.
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想想祖父钟或其他基于摆钟的滴答声。在这种情况下，完整的滴答和滴答周期通常为一秒。对于钟表，我们从重力和/或弹簧驱动的机械装置转变为水晶驱动的电力装置。某些晶体可以在电路中使用，从而产生电振荡。数字电子产品现在使用晶体，您可以获得高速和非常准确的计时。因此，本例中的时钟就是该晶体振荡器的电输出，一个 10,000,000Hz（或 10MHz）时钟意味着每秒有 1000 万次电滴答声。将其输入 AND、OR 和 NOT 逻辑，您就可以运行处理器和外设。
让我们将讨论限制在较旧的处理器或微控制器上，其中处理器和内存以及所有东西都使用相同的时钟。通过将此时钟信号馈送到数字逻辑，您可以拥有从内存读取指令并以某种派生速率执行这些指令的逻辑。从内存中加载一个值（读取）可能需要 3 个时钟周期，一个时钟周期用于从内存中获取指令，另一个时钟周期用于解码并开始执行该指令，并且因为该指令是从内存中读取的，内存不能同时做两件事（在这个模型中），那就是从内存中读取第三个时钟周期，然后读取并执行下一条指令，依此类推。因此，一些处理器由于这些原因而改变其执行时间，总是从存储器中获取指令并进行解码和执行，并且每个步骤都需要一个或多个时钟周期。某些处理器设计选择对每个指令周期使用固定的（假设）4 个时钟周期，该处理器的最长执行指令为 4 个时钟周期，有些可能只需要一个时钟周期。
然后事情变得更好，你听到管道这个词，你会看到 x86 能够每个时钟执行一条指令的广告，或者超标量，它每个时钟执行多个指令。这有点误导。如果您愿意，管道的作用就是创建一条装配线。想想工厂电视节目，它是如何制作的等等。制造挂锁的机器，沿着装配线有很多步骤，每个步骤执行一个简单的操作，在表盘上涂上数字，将表盘移到轴上，将表盘加轴插入装置中，等等。这是最后一步，看起来他们在装配线的每个周期制作一把锁，而实际上每个锁可能需要 30 个时钟。对于一个时钟周期上的处理器，管道上的一个成员从 RAM 中获取指令，下一个内存解码前一条指令，第三个内存在执行两条指令之前，依此类推。因此，当您听到刷新管道或管道停顿时，这是什么意思装配线已经停止，或者他们必须停止装配线并扔掉生产线上的所有物品并重新开始。传统上，当您有一条分支指令，这意味着它之后的两条或几条指令不会被执行时，您必须刷新管道并从分支所在的地址开始再次填充它。
如果您已经使用了足够长的时间或者进行了一些谷歌搜索或维基百科阅读，您将会听说 486DX 处理器。这是现在极为常见的事情的开始。在此之前，处理器中有一个基于单晶体振荡器的时钟，如果您希望以 16MHz 的频率运行处理器，则需要放置一个 16MHz 时钟。有几个问题，其中之一是内存接口无法跟上，一个非常简单的解决方案是您可以将处理器上的这些引脚并以较低的速率与内存通信，假设您的处理器以 16Mhz 运行，您可以运行通过创建一个主时钟速率一半的新时钟，以 8Mhz 运行内存。因此，从 16mhz 的滴答滴答开始，您仅在滴答时将输出更改为内存。因此，第一个内部滴答在内存总线时钟上滴答，第一个滴答，内存输出没有变化，第二个滴答在内存总线时钟上滴答，第三个滴答在内存上滴答，第四个滴答是滴答在内存总线上等等。真正的问题出现在 I/O 本身、处理器上的所有引脚无法以内部晶体管可以运行的时钟速率运行时。因此，对于 486DX，他们所做的是采用 25MHz 时钟，并使用一些模拟魔法将其转换为部件内部的 50MHz 时钟，部件的边缘、内存和其他总线以 25MHz 或更低的速度运行，但处理器，所以只要您能够足够快地提供指令（这会引发有关缓存的讨论），就会以 50MHz 运行管道。在没有停顿或刷新的突发情况下，每秒将有 5000 万条指令。在当时，创造一个稳定的 2 倍乘数是一件棘手的事情。但今天它相对微不足道。现代多千兆赫兹处理器不使用千兆赫兹时钟，它们通常使用 100MHz 左右的时钟，并将其扩展到处理器核心的几千兆赫兹，那么您可能会听到 800MHz DDR 内存或 1066MHz 内存或 1333 等。 100MHz 时钟也是如此参考相乘以创建内存总线的速度。
因此，在现代计算机中，与过去一样，您仍然使用基于晶体的振荡器作为时钟源，这是大自然的魔力，从中您可以为计算机周围的处理器和外围设备创建许多不同速度的时钟。例如，您可以通过谷歌搜索 USB 接口、火线和硬盘接口（ide/sata）等的各种时钟速率。
我已经看到您关于 PIC 编程的其他问题，例如，PIC 处于传统类型的模式中，其中所有内容以单个时钟速率运行单个时钟，如果您查看我的答案之一，您可以看到“时钟”周期的计数，并使用周期单位对它们进行计数。一旦完成，您就可以将一个时间单位应用于它的乘法或除法，具体情况可能是 4Mhz 时钟或 1MHz 时钟等。同一部分代码可能需要 100 个周期来执行，使用 4MHz 时钟的处理器将执行这 100 条指令的速度比使用 1MHz 振荡器快 4 倍。正如 drhirsch 所暗示的那样，它几乎是线性的，至少对于像这样的简单情况来说是这样。对于现代计算机，如果您使用相同的代码从同一硬盘驱动器读取数据，则 3GHz 处理器不会比 1GHz 处理器快 3 倍，因为硬盘驱动器速度相同，且 3GHz 处理器和 1GHz 处理器都停止运行等待硬盘数据。你可能有一辆法拉利出租车，但如果你住在一个长和宽均为 1 英里的城镇，居民年龄较大、速度较慢，那么你的法拉利大部分时间都会停在装载和卸载乘客的地方，并且不会超速行驶几百码。小型货车实际上比法拉利更快（让人们进出是瓶颈）。
Think of the tick-tock sound of a grandfather or other pendulum based clocks. A complete tick and tock cycle is usually one second in that case. And with clocks and watches we went from gravity and/or spring powered mechanical to something crystal powered electrical. Certain crystals can be used in circuits in such a way that they create an electrical oscillation. Digital electronics now use crystals as well as you can get high speed and very accurate timing. So the clock in this case is the electrical output of this crystal oscillator, a 10,000,000Hz (or 10MHz) clock means there are 10 million electrical tick-tocks per second. Feed that into AND, OR, and NOT logic and you can run processors and peripherals.
Lets limit the discussion for a second to older processors or microcontrollers, something where the processor and the memory and everything uses the same clock. With this clock signal feeding the digital logic you can have logic that reads instructions from memory and executes those instructions at some derived rate. Loading a register with a value from memory (a read) may take 3 clock cycles, one clock cycle to fetch the instruction from memory, another clock cycle to decode and begin to execute that instruction, and because the instruction is a read from memory and the memory cannot do two things at once (in this model) then that is a third clock cycle to read from memory, then the next instruction is read and executed and so on. So some processors vary their execution time for these reasons, there is always a fetch of the instruction from memory and a decode and execute, and each of these steps takes one or more clock cycles. Some processor designs choose to use a fixed lets say 4 clock cycles for every instruction cycle with the longest executing instruction for that processor being 4 clock cycles, and some may take only one clock cycle.
Then things got better and you hear the word pipeline, and you see advertisements of an x86 being able to execute one instruction per clock or superscalar where it executes more than one instruction per clock. that is a bit misleading. What the pipeline does is create an assembly line if you will. think of the factory tv shows, how its made and others. The machine that makes padlocks, has many steps along the assembly line, each step performs one simple operation, paint the numbers on the dial, move the dial onto a shaft, insert the dial plus shaft into the unit, etc. if all you looked at was the last step it would look like they were making one lock per per cycle of the assembly line, when it may have actually taken 30 clocks per lock. With processors on one clock cycle one member on the pipeline fetches the instruction from ram, the next memory decodes the previous instruction, the third is executing two instructions ago, etc. So when you hear flushing a pipe or a pipeline stall what that is is the assembly line has stopped or they have to stop the assembly line and throw out every item on the line and start fresh. traditionally when you have a branch instruction that means the two or few instructions right after it are not going to be executed, you have to flush the pipe and start to fill it again from the address where the branch has lead.
If you have been around long enough or do some googling or wikipedia reading you will hear about the 486DX processor. It was the beginning of something that is extremely common now. Before that time there was a single crystal oscillator based clock into the processor, you wanted to run your processor at 16MHz you put a 16MHz clock. A few problems, one was that memory interfaces were not able to keep up, a very simple solution to that is you can take those pins on your processor and talk to the memory at a reduced rate, say your processor runs at 16Mhz you could run the memory at 8Mhz by creating a new clock that is half the rate of the main clock. So from the tick-tock-tick-tock at 16mhz you change the output to the memory only on the ticks. So the first internal tick puts a tick on the memory bus clock, the first tock, no change on the memory output, the second tick you put a tock on the memory bus clock, third tick a tick on the memory, fourth tick a tock on the memory bus and so on. The real problem came when the I/O itself, all of the pins on the processor were not able to run at the clock rate that transistors inside could run. So with the 486DX what they did was take a 25MHz clock, and using some analog magic turn that into a 50MHz clock inside the part, the edges of the part, the memory and other buses ran at 25MHz or slower, but the processor, so long as you could feed instructions fast enough (this leads into a talk about caches), would run the pipeline at 50MHz. In the bursts without stalls or flushing that would be 50 million instructions per second. Creating a stable 2x multiplier at the time was tricky business. but today it is relatively trivial. Modern multi giga hertz processors do not use gigahertz clocks they often use clocks around 100MHz and scale them up to a few gigahertz for the processor cores, then you may hear about 800mhz DDR memory or 1066MHz memory or 1333, etc. Same deal the 100MHz clock reference is multiplied up to create those speeds for the memory bus.
So in modern computers, as with the old days, you still use crystal based oscillators as a clock source, the magic of nature, from that you create many different speed clocks for the processor and peripherals around the computer. For example you can google the various clock rates for USB interfaces and firewire and hard disk interfaces (ide/sata), etc.
I have seen your other questions about PIC programming for example, the PIC, is in that traditional type of mode where everything runs off of a single clock at a single clock rate, and if you look at one of my answers there you can see the counting of the "clock" cycles, and count them using units of cycles. Once that is done then you can apply a unit of time to it multiply or divide as the case may be with a 4Mhz clock or 1MHz clock etc. The same section of code may take 100 cycles to execute, a processor using a 4MHz clock will execute those 100 instructions 4 times faster than if you used a 1MHz oscillator. As drhirsch implied it is almost linear, at least for simple cases like this. For modern computers if you are reading data from the same hard drive with the same code a 3ghz processor is not 3 times faster than a 1 ghz processor because the hard drive speed is the same slow speed and both the 3ghz processor and 1ghz processor are stalled waiting for data from the hard disk. You may have a taxi cab that is a ferrari, but if you live in a town with older, slower folks that is 1 mile long and wide, your ferrari is going to be parked most of the time loading and unloading passengers and not speeding for a few hundred yards. A minivan would actually be faster than the ferrari (getting folks in and out is the bottleneck).
在这种情况下，时钟频率或时钟速率是单个命令或最小不可分命令的速率执行CPU中的部分命令。它是时钟周期长度的倒数。
示例：
Z80 上的一个时钟周期持续 250 ns（因为其频率为 4 MHz），在 Phenom 上则持续 0.333 ns（其频率约为 3 GHz）。
在较旧的 Z80 中，将 8 位数据从一个 cpu 寄存器移动到另一个需要 4 个时钟周期，而在 phenom 中，相同的操作需要一个周期 - 并且最多可以并行执行 3 个这样的指令。
这显然取决于 CPU 的架构，并且对于给定的 CPU 类型，执行速度和时钟频率几乎呈线性相关。
In this context the clock frequency or clock rate is the rate, at which single commands or the smallest indivisible parts of commands in a CPU are executed. It is the inverse of the length of a clock cycle.
Examples:
One clock cycle on a Z80 lasts 250 ns (because of its frequency of 4 MHz), on a Phenom it lasts 0.333 ns (its frequency is about 3 GHz).
In an older Z80 moving 8 bit data from one cpu register to another needed 4 clock cycles, where in a phenom the same operation needs one cycle - and up to 3 such instruction can be done in parallel.
This depends obviously on the architecture of the CPU, and for a given cpu type there is a almost linear dependency of execution speed and clock frequency.