使用 Wire 或 reg 进行输入或输出
当您将某些内容声明为输入或输出时，您如何知道是否还必须将其声明为 reg 还是 wire？
When you declare something as input or output, how do you know if you have to also declare it as a reg or a wire?
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reg和wire指定如何分配对象，因此仅对输出有意义。如果您打算在顺序代码中分配输出，例如在
always块中，请将其声明为reg（这实际上是 Verilog 中“变量”的用词不当） 。否则，它应该是wire，这也是默认值。regandwirespecify how the object will be assigned and are therefore only meaningful for outputs.If you plan to assign your output in sequential code,such as within an
alwaysblock, declare it as areg(which really is a misnomer for "variable" in Verilog). Otherwise, it should be awire, which is also the default.output reg foo只是output foo_wire 的简写；注册富；分配 foo_wire = foo。当您打算注册该输出时，它会很方便。我认为input reg对于module（也许是task）没有意义。输入线和输出线与输入和输出相同：只是更明确。An
output reg foois just shorthand foroutput foo_wire; reg foo; assign foo_wire = foo. It's handy when you plan to register that output anyway. I don't thinkinput regis meaningful formodule(perhapstask).input wireandoutput wireare the same asinputandoutput: it's just more explicit.您使用的 Verilog 代码编译器将决定您必须做什么。如果使用非法语法，则会出现编译错误。
仅当使用“过程赋值”进行赋值时，
output也必须声明为reg。例如：无需将
output声明为wire。无需将
input声明为wire或reg。The Verilog code compiler you use will dictate what you have to do. If you use illegal syntax, you will get a compile error.
An
outputmust also be declared as aregonly if it is assigned using a "procedural assignment". For example:There is no need to declare an
outputas awire.There is no need to declare an
inputas awireorreg.在数字电路域中看到它
所以这完全取决于您的使用是否需要创建一个寄存器并根据敏感度列表勾选它或者您想要创建一个端口/引脚分配
seeing it in digital circuit domain
so it completely depends on your use whether you need to create a register and tick it according to sensitivity list or you want to create a port/pin assignment
基本上 reg 用于存储值。例如，如果您想要一个计数器（它将计数，因此每个计数都会有一些值），我们将使用 reg。
另一方面，如果我们只有一个带有 2 个值 0 和 1 的普通信号，我们会将其声明为 Wire。Wire 不能保存值。因此，为 Wire 分配值会导致问题......
basically reg is used to store values.For example if you want a counter(which will count and thus will have some value for each count),we will use a reg.
On the other hand,if we just have a plain signal with 2 values 0 and 1,we will declare it as wire.Wire can't hold values.So assigning values to wire leads to problems....