这两个模块的行为有何不同
这两个模块似乎可以互换。他们的行为有何不同？
module Add_half (sum, c_out, a, b);
input a, b;
output reg c_out;
output reg sum;
always@(a, b)
begin
sum = a ^ b;
c_out = a & b;
end
endmodule
module Add_half (sum, c_out, a, b);
input a, b;
output c_out, sum;
assign sum = a ^ b;
assign c_out = a & b;
endmodule
These two modules seem to be interchangeable. How does their behavior differ?
module Add_half (sum, c_out, a, b);
input a, b;
output reg c_out;
output reg sum;
always@(a, b)
begin
sum = a ^ b;
c_out = a & b;
end
endmodule
module Add_half (sum, c_out, a, b);
input a, b;
output c_out, sum;
assign sum = a ^ b;
assign c_out = a & b;
endmodule
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事件调度存在细微差别，这可能会导致在时间 0 处出现不同的行为。
当 a 或 b 在时间 0 处初始化为某个非 X 值时，always 块可能不会将其视为更改，因此可能会发生变化。不被触发。因此，输出可能与输入不一致。
相反，连续分配的输出将始终与其输入一致。
There are subtle differences in event scheduling, which may result in different behavior at time 0.
When a or b are initialized to a certain non-X value at time zero, the always block may not see that as a change, and hence it may not be triggered. Consequently, the outputs may be inconsistent with the inputs.
In contrast, the outputs of continuous assignments will always be consistent with their inputs.