为什么进程中我的 VHDL 组合逻辑存在延迟?

发布于 2024-10-20 15:24:50 字数 1676 浏览 1 评论 0原文

我正在为组合逻辑创建一个测试平台,其中 a、b、cin 是被测实例化单元的输入。一切似乎都运行良好。

然而,我通过在测试台进程​​中添加来导出 test_s 信号,这似乎被奇怪地延迟了。我的“等待”语句的持续时间并不重要,我可以将单位从 ps 更改为 ns,并且症状是相同的。似乎发生的情况是 a 和 b 设置正确,但 test_s 不会更改,直到 a 和 b 更改其值。发生这种情况时,test_s 实际上会更新为 a 和 b 的先前值。所以一开始当a和b变为0时,test_s变为XXXXXXX。然后,当 a 变为 1 时,test_s 变为 0000000,而实际上应该为 00000001。

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-- Instantiate the Unit Under Test (UUT)
   uut: FastCarry8 PORT MAP (
      a => a,
      b => b,
      cin => cinVec(0), 
      cout => cout
    );

   signal a : std_logic_vector(7 downto 0) := (others => '0');
   signal b : std_logic_vector(7 downto 0) := (others => '0');
   signal cinVec : std_logic_vector(1 downto 0);
   signal test_s : std_logic_vector(8 downto 0);

  -- Stimulus process
  stim_proc: process 
  begin     
  -- hold reset state
  wait for 10 ps;   

    carry_gen: for carry in 0 to 1 loop
        cinVec <= std_logic_vector(to_unsigned(carry, 2));

        b_gen: for j in 0 to 255 loop
            a_gen: for i in 0 to 255 loop

                a <= std_logic_vector(to_unsigned(i, 8));
                b <= std_logic_vector(to_unsigned(j, 8));
                test_s <= std_logic_vector(resize(unsigned(a), test_s'length) + 
                    unsigned(b) + unsigned(cinVec));

                wait for 5ps;

                ASSERT (test_s(8) = cout)
                    REPORT "Carry out failed for cin = 0!";

                wait for 5ps;

            end loop a_gen;
        end loop b_gen;
    end loop carry_gen;

I'm creating a testbench for combinational logic, where a, b, cin are inputs in to an instantiated unit under test. All that appears to be working fine.

However, I'm deriving a test_s signal through addition within my test bench process, and that seems to be strangely delayed. It doesn't matter the duration of my 'wait' statements, I can change the units from ps to ns and the symptoms are the same. What seems to be happening is that a and b set up properly, but test_s doesn't change until a and b change their values. When this happens, test_s actually updates to the previous values of a and b. So at first when a and b become 0, test_s becomes XXXXXXX. Then, when a becomes 1, test_s becomes 0000000 when it should actually be 00000001.

enter image description here

enter image description here

-- Instantiate the Unit Under Test (UUT)
   uut: FastCarry8 PORT MAP (
      a => a,
      b => b,
      cin => cinVec(0), 
      cout => cout
    );

   signal a : std_logic_vector(7 downto 0) := (others => '0');
   signal b : std_logic_vector(7 downto 0) := (others => '0');
   signal cinVec : std_logic_vector(1 downto 0);
   signal test_s : std_logic_vector(8 downto 0);

  -- Stimulus process
  stim_proc: process 
  begin     
  -- hold reset state
  wait for 10 ps;   

    carry_gen: for carry in 0 to 1 loop
        cinVec <= std_logic_vector(to_unsigned(carry, 2));

        b_gen: for j in 0 to 255 loop
            a_gen: for i in 0 to 255 loop

                a <= std_logic_vector(to_unsigned(i, 8));
                b <= std_logic_vector(to_unsigned(j, 8));
                test_s <= std_logic_vector(resize(unsigned(a), test_s'length) + 
                    unsigned(b) + unsigned(cinVec));

                wait for 5ps;

                ASSERT (test_s(8) = cout)
                    REPORT "Carry out failed for cin = 0!";

                wait for 5ps;

            end loop a_gen;
        end loop b_gen;
    end loop carry_gen;

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盛夏尉蓝 2024-10-27 15:24:50

必须在 a、b 的分配和 test_s 的分配之间等待,因为 test_s 取决于这些信号值..这是私下回答的

Had to put a wait between assignment of a,b and the assignment of test_s since test_s is depending on those signal values.. this was answered privately

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