VHDL中简单IF语句的数据类型问题
我有一个非常奇怪的问题，我并不是 100% 知道编译器抱怨的原因。代码如下：
variable a : std_logic_vector(2 downto 0);
variable b : std_logic;
....
if (a = "100") AND (b) then
-- do something
elsif (a = "011") OR (b) then
-- do something else
我收到错误消息：
"AND can not have such operands in this context",
"OR can not have such operands in this context", respectively for the second IF statement.
知道为什么 VHDL 不喜欢这种构造吗？是否有解决方法？
I have a really weird problem and I am not 100% why the compiler is complaining. The code is as follows:
variable a : std_logic_vector(2 downto 0);
variable b : std_logic;
....
if (a = "100") AND (b) then
-- do something
elsif (a = "011") OR (b) then
-- do something else
I get the error message:
"AND can not have such operands in this context",
"OR can not have such operands in this context", respectively for the second IF statement.
Any idea why VHDL does not like this construction and if there is a workaround for that?
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VHDL 是强类型的 - 在测试环境中它需要布尔值。尝试
(b = '1')。VHDL is strongly typed - in a test context it expects booleans. Try
(b = '1').您正在尝试将向量与位进行比较，其中之一是将代码稍微更改为：
if (a = "100") then
如果 (b) 则
——做某事
结束如果
elsif (a = "011") 然后
如果 (b) 则
——做点别的事
结束如果；
结束如果；
You are trying to compare a vector with bit, one was it to change your code slightly to:
if (a = "100") then
if (b) then
-- do something
end if
elsif (a = "011") then
if (b) then
-- do something else
end if;
end if;