Verilog 没有类似 main() 的东西吗？
我知道模块本质上就像 C++ 函数。但是，我没有找到类似 main() 部分的内容来调用这些函数。如果没有 main() 部分，它如何工作？
I understand that modules are essentially like c++ functions. However, I didn't find something like a main() section that calls those functions. How does it work without a main() section?
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尝试在 HDL 中找到（或概念上强制）等效的 main() 是学习 HDL 的错误方法 - 它会阻止您取得进步。对于可综合的描述，您需要从顺序思维（一条指令接着另一条指令运行）跨越到“并行”思维（一切都在始终运行）。从心理上来说，从左到右而不是从上到下查看代码，您可能会意识到 main() 的概念并不是那么有意义。
在HDL中，我们不“调用”函数，我们实例化模块并将其端口连接到网络；同样，你需要改变你对这个过程的看法。
一旦你掌握了它，一切都会变得更加顺利......
Trying to find (or conceptually force) a main() equivalent in HDL is the wrong way to go about learning HDL -- it will prevent you from making progress. For synthesisable descriptions you need to make the leap from sequential thinking (one instruction running after another) to "parallel" thinking (everything is running all the time). Mentally, look at your code from left to right instead of top to bottom, and you may realize that the concept of main() isn't all that meaningful.
In HDL, we don't "call" functions, we instantiate modules and connect their ports to nets; again, you'll need to change your mental view of the process.
Once you get it, it all becomes much smoother...
请记住，Verilog 的正常用途是建模/描述电路。当您通电时，所有电路都开始运行，因此您需要编写复位逻辑以使每个电路进入稳定、可用的操作状态。通常，您将包含一条重置线并进行初始化以响应该重置线。
Keep in mind that the normal use of Verilog is modeling/describing circuits. When you apply power, all the circuits start to run, so you need to write your reset logic to get each piece into a stable, usable operating state. Typically you'll include a reset line and do your initialization in response to that.
Verilog 有
initial块，有点像 C 中的main()。这些是计划从时间 0 开始运行的语句列表。Verilog 可以有多个initial< /code> 块虽然是并发执行的。如果
always块的敏感度列表为空，它们也将用作main()：Verilog has
initialblocks are kinda likemain()in C. These are lists of statements that are scheduled to run from time 0. Verilog can have multipleinitialblocks though, that are executed concurrently.alwaysblocks will also work asmain()if they've an empty sensitivity list: