关于 XST 比特流生成的问题
我有一个非常简单的 VHDL 模块，由几行代码组成。问题是，当我生成比特流时，我结束了 具有巨大的比特流。我猜这是因为 XST 添加了很多额外的信息，以便比特流 可以在 FPGA 上独立运行。
然而，就我的目的而言，单独查看模块比特流的大小而不需要任何额外的位和片段，仅使用 vaniall 模块会很有趣。 Xilinx ISE 12.1 中是否有一个选项允许我执行此操作？
非常感谢， 里奇
I have a very simple VHDL module, consisting of a few lines of code. The thing is, when I generate the bitstream, I end
up with a huge bitstream. The reason for this is, I guess, that XST adds lots of extra information so that the bitstream
can run standalone on a FPGA.
However, for my purpose it would be interesting to see the size of the bitstream of the module alone without any extra bits and pieces, just the vaniall module alone. Is there an option in Xilinx ISE 12.1 that allows me to do that?
Many thanks,
Richi
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比特流包含您所针对的设备的每个可配置资源的信息，无论您的实际设计用途如何。当您对 FPGA 进行编程时，位文件会被记录到器件中，从而配置您未使用和正在使用的部件。因此，位文件的大小完全由目标设备决定。
如果您想查看模块正在使用的资源的详细信息，请查看由 map 生成的 .mrp 文件中的“第 14 节 - 按层次结构使用”部分。
The bitstream contains information for every configurable resource of the device you are targeting regardless of your actual design utilisation. When you program the FPGA the bitfile is clocked into the device, configuring the parts you are not using as well as the ones you are. The size of the bitfile is therefore dictated entirely by the target device.
If you want to see a breakdown of the resources your module is using, take a look at section "Section 14 - Utilization by Hierarchy" in the .mrp file generated by map.
正如 Chiggs 所说，对于您所针对的每个设备，比特流的大小始终相同。 （您可以通过打开 fpga_editor，保存一个空的 NCD 文件并转换为比特流来看到这一点......仍然是相同的大小！）或者，换句话说，必须设置每个配置存储单元（使用0 或 1) 配置。
但实际上，您可以按照您的要求进行操作。这称为动态重新配置，为此，工具将生成比特流片段，这些片段一起构成整个比特流。首先，您使用常规比特流配置设备，然后您可以在 FPGA 的其余部分正常运行时动态地重新配置其上的比特流片段！ （整洁，不是？）
无论如何，这就是你所要求的，但我不确定这就是你想要的......你想要实现什么？
As Chiggs said, the bitstream is always the same size for each device you're targeting. (You can see this by opening fpga_editor, saving an empty NCD file and converting into a bitstream... still the same size!) Or, in other words, every configuration memory cell must be set (with 0 or 1) on configuration.
But, in fact, you could do what you're asking. It's called dynamic reconfiguration, and for this the tools will generate bitstream pieces that together make an entire bitstream. First you configure the device with a regular bitstream and then you're able to dynamically reconfigure bitstream pieces on top of it while the rest of the FPGA is running normally! (Neat, no?)
Anyway, that's what you asked for, but I'm not sure that's what you wanted... what were you trying to achieve?
很抱歉介入讨论，但我认为 250KB 无论如何都不是一个巨大的比特流！我使用具有 3500 个逻辑片的非常小的 FPGA，它为我提供了 3MB 的比特流。这里需要考虑一件重要的事情。如果您尝试初始化任何 RAM，则比特流将携带额外的位，这些位是 FPGA 中 BRAM 块的初始化位。这只会向比特流添加额外的内存。但平均而言，整个 FPGA 矩阵是用存储在存储位文件的片外/片内闪存中的位进行写入的，因此它不应在每次运行时发生变化。
Sorry for jumping into the discussion but I do not think 250KB is a huge bitstream in any way! I use a very small FPGA of 3500 Logic slices and it gives me a bitstream of 3MB. One important thing to consider here. If you are trying to initialize any of your RAMs then the bitstream is going to carry extra bits which are initialization bits of the BRAM Blocks in the FPGA. that can just add additional memory to the bitstream. But on an average, it is the whole FPGA matrix that is getting written with the bits stored in the Offchip/OnChip Flash where the bitfile is stored, So it should not change from run to run.