直接内存访问 DMA - 它是如何工作的？
我读到，如果 DMA 可用，那么处理器可以将磁盘块的长读取或写入请求路由到 DMA 并专注于其他工作。但是，在此传输期间，DMA 到内存数据/控制通道正忙。在此期间处理器还能做什么？
I read that if DMA is available, then processor can route long read or write requests of disk blocks to the DMA and concentrate on other work. But, DMA to memory data/control channel is busy during this transfer. What else can processor do during this time?
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首先，DMA（本身）几乎完全过时了。正如最初定义的那样，DMA 控制器依赖于总线具有单独的线路来断言内存读/写和 I/O 读/写的事实。 DMA 控制器利用了这一点，同时声明内存读取和 I/O 写入（反之亦然）。然后，DMA 控制器在总线上生成连续的地址，并且在每个总线周期从存储器读取数据并将其写入输出端口（反之亦然）。
然而，PCI 总线没有有单独的线路用于内存读/写和 I/O 读/写。相反，它为任何给定事务编码一个（且仅一个）命令。 PCI 通常不使用 DMA，而是进行总线主控传输。这意味着 I/O 设备本身直接将数据传输到内存或从内存传输数据，而不是在 I/O 设备和内存之间传输内存的 DMA 控制器。
至于CPU当时还能做什么，那就要看情况了。当 DMA 很常见时，答案通常是“不多”——例如，在早期版本的 Windows 下，读取或写入软盘（确实使用 DMA 控制器）几乎会在一段时间内锁定系统。
然而，现在内存的带宽通常比 I/O 总线大得多，因此即使外设正在读取或写入内存，通常也会留下相当多的带宽供 CPU 使用。此外，现代 CPU 通常具有相当大的高速缓存，因此它通常可以执行某些指令而不使用主内存。
First of all, DMA (per se) is almost entirely obsolete. As originally defined, DMA controllers depended on the fact that the bus had separate lines to assert for memory read/write, and I/O read/write. The DMA controller took advantage of that by asserting both a memory read and I/O write (or vice versa) at the same time. The DMA controller then generated successive addresses on the bus, and data was read from memory and written to an output port (or vice versa) each bus cycle.
The PCI bus, however, does not have separate lines for memory read/write and I/O read/write. Instead, it encodes one (and only one) command for any given transaction. Instead of using DMA, PCI normally does bus-mastering transfers. This means instead of a DMA controller that transfers memory between the I/O device and memory, the I/O device itself transfers data directly to or from memory.
As for what else the CPU can do at the time, it all depends. Back when DMA was common, the answer was usually "not much" -- for example, under early versions of Windows, reading or writing a floppy disk (which did use the DMA controller) pretty much locked up the system for the duration.
Nowadays, however, the memory typically has considerably greater bandwidth than the I/O bus, so even while a peripheral is reading or writing memory, there's usually a fair amount of bandwidth left over for the CPU to use. In addition, a modern CPU typically has a fair large cache, so it can often execute some instruction without using main memory at all.
需要注意的关键点是，CPU 总线始终部分由 DMA 使用，而通道的其余部分可自由用于任何其他作业/进程的运行。这是 DMA 相对于 I/O 的主要优势。希望这能回答您的问题:-)
Well the key point to note is that the CPU bus is always partly used by the DMA and the rest of the channel is free to use for any other jobs/process to run. This is the key advantage of DMA over I/O. Hope this answered your question :-)
忙碌并不意味着您已经饱和并且无法进行其他并发传输。确实，内存的响应速度可能比正常情况要慢一些，但 CPU 仍然可以做有用的工作，而且它们还可以畅通无阻地做其他事情：处理缓存中已经存在的数据、接收硬件中断等。这不仅仅是关于数据量，但生成的速率：某些设备以硬实时方式创建数据，需要立即使用它，否则数据会被覆盖和丢失：要在没有 DMA 的情况下处理此问题，软件可能必须将自己钉在一个然后，CPU 核心旋转等待和读取 - 避免在整个调度程序时间片内交换到其他任务 - 即使大多数时候进一步的数据甚至还没有准备好。
Being busy doesn't mean you're saturated and unable to do other concurrent transfers. It's true the memory may be a bit less responsive than normal, but CPUs can still do useful work, and there are other things they can do unimpeded: crunch data that's already in their cache, receive hardware interrupts etc.. And it's not just about the quantity of data, but the rate at which it's generated: some devices create data in hard real-time and need it to be consumed promptly otherwise it's overwritten and lost: to handle this without DMA the software may may have to nail itself to a CPU core then spin waiting and reading - avoiding being swapped onto some other task for an entire scheduler time slice - even though most of the time further data's not even ready.
在 DMA 传输期间，CPU 处于空闲状态，无法控制内存总线。利用高阻态将CPU置于空闲状态
During DMA transfer, the CPU is idle and has no control over memory bus. CPU is put in idle state by using high impedance state