VHDL 中的语法错误
我正在尝试使用结构 VHDL 和组件来实现一位计数器。 我在尝试进行端口映射时遇到语法错误。 错误为“错误 (10028)：无法解析分配4.vhd(47) 处的网络“P”的多个常量驱动程序” 这是我到目前为止所拥有的： 预先感谢您的任何想法。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------
Entity Assign4 is
Generic (bits: POSITIVE := 1);
Port (CLK: in std_logic;
SE1,SE2: in std_logic;
P: out std_logic);
End Entity Assign4;
---------------------------------------------------------------
Architecture Structural of Assign4 is
--------------------------------
Component Counter is
-- Generic (N: Positive := 1);
Port(clock,sel1,sel2: in std_logic;
Q: out std_logic);
End Component;
--------------------------------
Signal x,y,z: std_logic;
begin
P <= x;
--Qn <= x;
process(CLK)
begin
if (Clk'event and CLK = '1') then
x <= x xor (SE1 and SE2);
end if;
end process;
--------------COUNTER-------------------------------------
count1: Counter PORT MAP (clk,SE1,SE2,P);
---------------END COUNTER--------------------------------
-- The generate will be used later for implementing more bits in the counter
--gen: FOR i IN 0 TO 1 GENERATE
-- count1: Counter PORT MAP (SE1 <= inbits(0),SE2 <= inbits(1),clock <= CLK,
-- outA <= SE1 and SE2, q <= outA xor q);
--end GENERATE gen;
---------------------------------------------------
end Architecture;
I am trying to implement a one bit counter using structural VHDL and components.
I am getting a syntax error when trying to do the port map.
The error is "Error (10028): Can't resolve multiple constant drivers for net "P" at Assign4.vhd(47)"
Here is what I have so far:
Thank you in advance for any ideas.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------
Entity Assign4 is
Generic (bits: POSITIVE := 1);
Port (CLK: in std_logic;
SE1,SE2: in std_logic;
P: out std_logic);
End Entity Assign4;
---------------------------------------------------------------
Architecture Structural of Assign4 is
--------------------------------
Component Counter is
-- Generic (N: Positive := 1);
Port(clock,sel1,sel2: in std_logic;
Q: out std_logic);
End Component;
--------------------------------
Signal x,y,z: std_logic;
begin
P <= x;
--Qn <= x;
process(CLK)
begin
if (Clk'event and CLK = '1') then
x <= x xor (SE1 and SE2);
end if;
end process;
--------------COUNTER-------------------------------------
count1: Counter PORT MAP (clk,SE1,SE2,P);
---------------END COUNTER--------------------------------
-- The generate will be used later for implementing more bits in the counter
--gen: FOR i IN 0 TO 1 GENERATE
-- count1: Counter PORT MAP (SE1 <= inbits(0),SE2 <= inbits(1),clock <= CLK,
-- outA <= SE1 and SE2, q <= outA xor q);
--end GENERATE gen;
---------------------------------------------------
end Architecture;
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评论（2）
错误消息是相当不言自明的：您从两个不同的地方驱动 P：
并且
（在计数器组件中，您已将最后一个端口列为输出，因此它也在驱动 P。）
我不能说出您的哪个陈述想要，尽管很可能是后者；您需要注释掉第一个分配，这将解决此编译错误。
The error message is fairly self-explanatory: you are driving P from two different places:
and
(In the Counter component, you've listed the last port as an output, so it is driving P also.)
I cannot say which statement you want, though likely it is the latter; you'll want to comment out the first assignment, which will resolve this compilation error.
在端口映射语句中，语法是
箭头指向错误的方向。
in port map statements, the syntax is
your arrows are pointing the wrong way.