我的 VHDL 语句可以吗？

发布于 2024-10-16 16:52:40 字数 675 浏览 0 评论 0原文

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_1164_unsigned.all;

ENTITY alu IS
    PORT (a: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
          b: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
          operation: IN INTEGER (1 TO 10);
          result: OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
    );

ARCHITECTURE arch-alu OF alu IS
    SIGNAL arith, logic: STD_LOGIC_VECTOR (15 DOWNTO 0);
    BEGIN
----rest of the code which give values to arith and logic----
    WITH operation SELECT
        result <= arith WHEN (1 TO 5),
                  logic WHEN (6 TO 10);
END arch-alu

我的问题是：我可以在 WHEN 之后放置一个范围（如代码中所示），或者我必须一一指定信号的每种可能性。

谢谢！

原文

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_1164_unsigned.all;

ENTITY alu IS
    PORT (a: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
          b: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
          operation: IN INTEGER (1 TO 10);
          result: OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
    );

ARCHITECTURE arch-alu OF alu IS
    SIGNAL arith, logic: STD_LOGIC_VECTOR (15 DOWNTO 0);
    BEGIN
----rest of the code which give values to arith and logic----
    WITH operation SELECT
        result <= arith WHEN (1 TO 5),
                  logic WHEN (6 TO 10);
END arch-alu

My query is: Can I put a range after WHEN (as in the code), or I have to specify one by one each possibility of the signal.

Thanks!

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-柠檬树下少年和吉他 2024-10-23 16:52:40

根据 http://tams-www.informatik .uni-hamburg.de/vhdl/tools/grammar/vhdl93-bnf.html 您使用的语法是 VHDL '93 允许的（要查看的结果按顺序为：selected_signal_assignment、selected_waveforms、choices 、 choice、discrete_range、range），但那里的语法似乎不允许在范围周围使用括号。另请参阅http://www.vhdl.renerta.com/source/vhd00063.htm （再次在范围周围没有括号）。

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凉薄对峙 2024-10-23 16:52:40

您可以在选择中使用范围，但应省略括号。

并不是说您的代码片段包含的错误不仅仅是多余的括号。您缺少结束实体、端口声明末尾有多余的分号以及不正确的整数端口声明，...一个好的 VHDL IDE，例如 Sigasi HDT，将帮助您立即抓住这些。
在此处输入图像描述
更正的片段：

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY alu IS
    PORT (a: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
          b: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
          operation: IN INTEGER range 1 TO 10;
          result: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
    );
end entity;

ARCHITECTURE arch_alu OF alu IS
    SIGNAL arith, logic: STD_LOGIC_VECTOR (15 DOWNTO 0);
    BEGIN
--rest of the code which give values to arith and logic----
    WITH operation SELECT
        result <= arith WHEN 1 TO 5,
                  logic WHEN 6 TO 10;
END arch_alu;

You can use ranges in choices but you should omit the parentheses.

Not that your code fragment contained a lot more errors than just the superfluous parentheses. You had a missing end entity, a superfluous semicolon at the end of the port declaration, and incorrect integer port declaration,... A good VHDL IDE, such as Sigasi HDT, would help you catch these immediately.
enter image description here
Corrected fragment:

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY alu IS
    PORT (a: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
          b: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
          operation: IN INTEGER range 1 TO 10;
          result: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
    );
end entity;

ARCHITECTURE arch_alu OF alu IS
    SIGNAL arith, logic: STD_LOGIC_VECTOR (15 DOWNTO 0);
    BEGIN
--rest of the code which give values to arith and logic----
    WITH operation SELECT
        result <= arith WHEN 1 TO 5,
                  logic WHEN 6 TO 10;
END arch_alu;

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