寻找verilog 2001模块声明语法

发布于 2024-10-16 06:53:40 字数 826 浏览 3 评论 0原文

我可以通过 google 找到几个 v2k 完整语法——但要么我失去了理智，要么它们在端口声明方面都以同样的方式被破坏了。输入示例：

module foo ( 
    input x, 
     output [2:0] y);
endmodule;

我找不到可以解析该语法的语法，但他们会接受这样的东西作为 list_of_port 中的“端口”：

         { name[3:0], name2[2:0]} 
.. or ..   .name( othername )

即我期望在模块实例化端口绑定的语法中看到的内容是为模块端口声明提供的。

示例

http://www.externsoft.ch/download/verilog.html#module_declaration

http://www.syncad.com/VeriLogger_bnf_Syntax_Verilog_2001.htm#list_of_ports

我想我可以查看 icarus 源代码，或 Perl::Verilog。不过，我希望得到上面的语法被破坏的确认——或者有人可以指出我错过了什么，如果没有的话。正确语法的来源会很棒......

原文

I can find several v2k full grammars with google -- but either I am losing my mind or they are all broken in the same way with regard to port declarations.
Example input:

module foo ( 
    input x, 
     output [2:0] y);
endmodule;

I can't find a grammar which will parse that syntax, but they will accept things like this
as a 'port' in the list_of_port:

         { name[3:0], name2[2:0]} 
.. or ..   .name( othername )

I.e. things I expect to see in the grammar for a module instantiation port binding are supplied for a module port declaration.

Examples

http://www.externsoft.ch/download/verilog.html#module_declaration

http://www.syncad.com/VeriLogger_bnf_Syntax_Verilog_2001.htm#list_of_ports

I guess I can look into the icarus source, or Perl::Verilog. I'm hoping to get a confirmation that the grammars above are broken, though -- or can someone point out what I'm missing if not. A source for a correct grammar would be great...

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℡Ms空城旧梦 2024-10-23 06:53:40

您的第一个代码块使用 list_of_port_declarations 语法，该语法在 IEEE 1364-2001(Sec 12.3.3) 和所有更高版本中有效。第一个链接的语法不完整，第二个链接看起来包含此构造

第二个代码块绝对有效。看起来像模块定义中的实例端口的语法是显式端口构造。不经常使用，当您想要在外部呈现与内部使用的信号接口不同的信号接口时，可以使用它们。下面是一些示例：

module mod1(portA);
input portA; //Implicit port named portA connected to implicit wire portA
endmodule

这里，portA 是隐式的，并且继承了输入声明的属性，因为它共享相同的标识符 portA。

module mod2(.expA(sigA));
wire sigA;
endmodule

module top;
wire sigB;
mod2 modInst(.expA(sigB));
endmodule

在此示例中，我们为 mod2 模块使用显式端口。 expA 在内部连接到 sigA，但正如您在实例 modInst 中看到的，我们使用外部名称进行命名连接。

module mod3 (.expA({sigC,sigD}), sigF, .expB(sigG[1],sigB[3:0]));
output reg [3:0] sigC, sigD;
input wire [1:0] sigG;
input wire [7:0] sigB;
output wire sigF;
endmodule

这也是有效的。端口 expA 假定 sigC 和 sigD 连接的宽度。与端口 expB 相同。

Your first code block uses the list_of_port_declarations syntax which is valid in IEEE 1364-2001(Sec 12.3.3) and all later versions. The grammar from the first link is incomplete, the second link looks like it includes this construct

Your second code block is definitely valid. The syntax that looks like instance ports in a module definition are explicit port constructs. Not used very often, these are used when you want to present a different signal interface externally than what is used internally. Here are a few examples:

module mod1(portA);
input portA; //Implicit port named portA connected to implicit wire portA
endmodule

Here, portA is implicit and inherits the attributes from the input declaration because it shares the same identifier portA.

module mod2(.expA(sigA));
wire sigA;
endmodule

module top;
wire sigB;
mod2 modInst(.expA(sigB));
endmodule

In this example we use an explicit port for the mod2 module. Internally expA is connected to sigA but as you see in the instance modInst, we use the external name for named connections.

module mod3 (.expA({sigC,sigD}), sigF, .expB(sigG[1],sigB[3:0]));
output reg [3:0] sigC, sigD;
input wire [1:0] sigG;
input wire [7:0] sigB;
output wire sigF;
endmodule

This is also valid. Port expA assumes the width of the sigC and sigD concatenation. Same with port expB.

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