Xilinx ISE 块 RAM 推理的稳健性
我对 Xilinx ISE block ram 推理的鲁棒性有疑问。
我的机器上没有安装 xilinx ise（今天），但我通常使用专用编码完美地推断 block ram，基本上依赖于：
type ram_type is array(2**ADDR_WIDTH-1 downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0);
我的问题是：你能告诉我 ISE 是否会推断出正确的 block ram
signed(DATA_WIDTH-1 downto 0)` instead of `std_logic_vector(DATA_WIDTH-1 downto 0)
甚至更多（在一个包中）：
subtype signed8 is signed(7 downto 0)
然后
type ram_type is array(2**ADDR_WIDTH-1 downto 0) of signed8;
我知道合成器有时很敏感......
I have a question regarding the robustness of Xilinx ISE block ram inference.
I don't have xilinx ise installed on my machine (today) but I usually infer block rams perfectly using a dedicated coding, basically relying on :
type ram_type is array(2**ADDR_WIDTH-1 downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0);
My question is : could you tell me if ISE will infer a correct block ram with
signed(DATA_WIDTH-1 downto 0)` instead of `std_logic_vector(DATA_WIDTH-1 downto 0)
or even more (in a package):
subtype signed8 is signed(7 downto 0)
and then
type ram_type is array(2**ADDR_WIDTH-1 downto 0) of signed8;
I know the synthesizers are sometimes touchy...
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我自己没有测试过，但“signed”类型是从 std_logic 类型派生的，所以我不明白为什么这不起作用。
假设您使用 XST 进行综合，XST 用户指南是了解 Xilinx 官方声明 XST 将识别 block ram 推理的好地方。 12.4 版 XST 用户指南 (pdf)
I haven't tested this myself, but the "signed" type is derived from the std_logic type, so I don't see why this shouldn't work.
Assuming you are using XST for synthesis, the XST user guide is a good place to start to see what Xilinx officially states XST will recognize for block ram inference. XST User Guide for 12.4 (pdf)
这是一般性评论，并非针对您的问题。试图对综合工具进行假设性的二次猜测并不是很有成效。结果可能会因工具版本以及设计和实施的环境（不同的开关、优化目标、目标架构等）而异。ISE/XST 是免费的...下载并尝试您的代码。然后你可以更有意义地问这个问题......“为什么 XST 版本 XY 在这些条件下不能推断出 Block RAM？”然后我们还可以讨论 XST 是否具有正确且预期的行为。
This is a general comment, not specific to your problem. Trying to hypothetically second guess a synthesis tool isn't very productive. Results can vary with tool versions and the context of your design and implementation (different switches, optimization goals, target architecture, etc.) ISE/XST is free... download it and try your code. Then you could ask the question more meaningfully... "Why does XST version X.Y not infer a Block RAM under these conditions?" Then we can also discuss whether XST has the correct and expected behaviour or not.
除了 Josh 建议的链接（详细介绍了 XST 的 RAM 实现）之外，这里还有 Xilinx 网站上的另一个文档，其中解释了不同的 RAM 实现及其权衡（第 76 页）：
http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/sim.pdf
作为旁注，我使用了“数组”方法，并且对于小块 RAM 大小非常有效。但是，我不得不说，我尝试使用它生成一个比我的 Spartan-6 中 1 个 BlockRAM 的大小大得多的内存模块，但它无法推断它（XST 尝试将其实现为分布式 RAM）。我通过直接实例化 Xilinx 提供的 BlockRAM 宏并创建适当的内存解码模块来选择/写入/读取内存模块中适当的各个 BlockRAM，从而解决了该问题。
Besides the link Josh suggested (which goes in detail about RAM implementation by XST), here is another document at Xilinx's Website, which explains different RAM Implementations and their tradeoffs (page 76):
http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/sim.pdf
As a side note, I have used the "array" approach and worked great for small Block RAM sizes. But, I have to say that I tried using it to generate a Memory Module that was much larger than the size of 1 BlockRAM in my Spartan-6 and it couldn't infer it (XST tried to implement it as Distributed RAM). I solved the problem by directly instantiating the BlockRAM Macros Xilinx's provide and by creating the proper memory decoding modules to select/write/read to the appropriate individual BlockRAMs in the Memory Module.