Verilog 数组语法
我是 Verilog 新手，并且遇到了很多麻烦。例如，我想要一个包含八个单元的数组，每个单元都是 8 位宽。以下内容不起作用：
reg [7:0] transitionTable [0:7];
assign transitionTable[0] = 10;
仅执行 transitionTable[0] = 10; 或 transitionTable[0] = 8'h10; 也不起作用 有什么想法吗？
（如果它不明显且不相关：我想制作一个有限状态机，并在数组中指定状态转换，因为这看起来比大规模的情况切换更容易。）
I'm new to Verilog, and am having a lot of trouble with it. For example, I want to have an array with eight cells, each of which is 8 bits wide. The following doesn't work:
reg [7:0] transitionTable [0:7];
assign transitionTable[0] = 10;
neither does just doing transitionTable[0] = 10; or transitionTable[0] = 8'h10; Any ideas?
(In case it is not obvious and relevant: I want to make a finite state machine, and specify the state transitions in an array, since that seems easier than a massive case switch.)
如果你对这篇内容有疑问，欢迎到本站社区发帖提问 参与讨论，获取更多帮助，或者扫码二维码加入 Web 技术交流群。
绑定邮箱获取回复消息
由于您还没有绑定你的真实邮箱，如果其他用户或者作者回复了您的评论，将不能在第一时间通知您！
发布评论
评论（4）
使用
assign时，您应该将数组声明为wire而不是reg。When using
assignyou should declare the array as awireinstead of areg.由于您的目标是设计 FSM，因此无需将状态值存储在数组中。这通常是使用 Verilog
parameter's、state寄存器和带有case/endcase语句的next_state来完成的。以下论文显示了一个完整的示例：FSM 基础
Since your goal is to design an FSM, there is no need to store the state values in an array. This is typically done using Verilog
parameter's, astateregister and anext_statewith acase/endcasestatement.The following paper shows a complete example: FSM Fundamentals
如果这是针对综合：
稍微超出上面回答的内容，您应该遵守标准的 FSM 编码风格，以便工具可以执行更好的优化。正如 Cummings 论文中所述，one-hot 通常最适合 FPGA 设备，事实上 ISE（使用默认设置）会忽略您的编码并实施它认为最能充分利用设备资源的任何方式。无论您选择哪种状态编码，只要它能够识别您的 FSM，这几乎总是会导致单热编码的 FSM。
If this is targeted towards synthesis:
A little beyond what was answered above, there are standard FSM coding styles that you should adhere to so the tools can perform better optimization. As described in the Cummings paper, one-hot is usually best for FPGA devices and in fact ISE(with default settings) will ignore your encoding and implement whatever it thinks will best utilize the resources on the device. This almost invariably results in a one-hot encoded FSM regardless of the state encoding you chose, provided it recognizes your FSM.
好的，为了回答您的问题，让我们更深入地了解 Verilog 语法。
首先，要指定位范围，请执行
[MSB:LSB]或[LSB:MSB]。标准是 MSB:LSB，但这实际上取决于您，但请尽量保持一致。接下来，在数组实例化中，我们有：
reg WIDTH reg_name NUMBER;，其中
WIDTH是每个元素的“大小”，NUMBER是元素的数量。数组中的元素。因此，您首先要做：
reg [7:0]transitionTable [7:0];然后，要分配特定字节（8 位 = 1 字节），请执行以下操作：
一本学习 Verilog 的好书来自 Pong P. Chu 的FPGA Prototyping By Verilog Examples。
OK, so to answer your question, let's dig a little deeper into Verilog syntax.
First of all, to specify a range of bits, either do
[MSB:LSB]or[LSB:MSB]. The standard isMSB:LSBbut it is really up to you here, but try to be consistent.Next, in array instantiation we have:
reg WIDTH reg_name NUMBER;where
WIDTHis the "size" of each element andNUMBERis the number of elements in the array.So, you first want to do:
reg [7:0] transitionTable [7:0];Then, to assign particular bytes (8 bits = 1 byte), do:
A good book to learn Verilog from is FPGA Prototyping By Verilog Examples by Pong P. Chu.