VHDL 的 TAP(测试任何协议)模块
是否有 VHDL 的 TAP(测试任何协议)实现?那就太好了,因为这样我就可以使用证明来自动检查我的结果。还有一些很好的格式化 swuites,例如 smolder 可以处理它输出。您可能会问为什么不使用断言。部分 TAP 为我提供了一些很好的报告,例如文件数量和测试数量。我正在寻找一个最小的实现,在开始和结束时进行大量测试以及确定、诊断和失败功能。 is() 确实很好,但不是必需的。我可以写这个,但为什么要重新发明轮子呢?
Is there a TAP (Test Anything Protocol) implementation for VHDL? It would be nice because then I could use prove to check my results automatically. There are also nice formatting swuites such as smolder that can process it output. You might ask why not use assertions. Partly TAP gives me some good reporting such as number of files and number of tests. I'm looking for a minimal implentation with number of tests at the beginning and end and the ok, diag and fail functions. is() would really nice, but not necessary. I could write this, but why reinvent the wheel.
This is the question as in this question but for VHDL instead of Verilog.
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我写了一篇我经常使用的文章,但我从未分发过它。就是这样(未包含的 base_pkg 大部分都有 to_string() 实现)。
I wrote one that I've used a lot, but I've never distributed it. Here it is (the not-included base_pkg mostly has to_string() implementations for everything).
从我有限的对 TAP 的快速阅读来看——不太可能......因为大多数 HDL 设计者与软件测试领域的联系并不那么紧密(尽管他们早在单元测试被称为单元测试之前就已经开始进行了:)我喜欢感觉自己是一名 HDL 设计师, 与软件测试领域有着相当密切的联系,但我以前从未接触过 TAP。我一直坚持使用 Python 自己的单元测试功能(并涉足 pytest)。以及我自己使用 VHDL 及其断言的混合物。
不过,它看起来像是一个相当简单的
包
...如果您决定自己编写一个包,请告诉我们!From my limited quick reading up on TAP - unlikely... because most HDL designers are not that well-connected with the world of software testing (even though they've been doing unit-testing since well before it was called that :) I like to feel I am an HDL designer who is reasonably well-connected to the world of software testing, and I've never come across TAP before. I've stuck to Python's own unittest functionality (and dabbled with pytest). And my own concoction for working with VHDL and its asserts.
It looks like a fairly simple
package
to write though... do let us know if you decide to write one yourself!