Quartus 中的 RTL 查看器中如何显示变量？
Quartus 的 RTL 查看器中如何描述变量。我打开 RTL 查看器，它没有显示任何变量寄存器。
例如：
variable op_code : std_logic_vector(7 downto 0);
RTL 查看器不会在 RTL 查看器中显示 op_code 是否有原因？我正在使用VHDL。
编辑：
op_code(7 downto 0) <=instr_reg(31 downto 24);
if ( op_code = ADD or op_code = MYSUB) then <br>
C_addr <= instr_reg(14 downto 10); <br>
end if;
CASE op_code(7 downto 0) IS
--some case statments
END CASE;
How is a variable depicted in a RTL viewer in Quartus. I open RTL viewer and it does not show any register for a variable.
For example:
variable op_code : std_logic_vector(7 downto 0);
Is there a reason why RTL viewer will not show op_code in RTL viewer? I am using VHDL.
Edit:
op_code(7 downto 0) <=instr_reg(31 downto 24);
if ( op_code = ADD or op_code = MYSUB) then <br>
C_addr <= instr_reg(14 downto 10); <br>
end if;
CASE op_code(7 downto 0) IS
--some case statments
END CASE;
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是不是已经被优化掉了？如果操作码的元素用于其他用途，它们可能已被纳入其他逻辑中，并且本身不再可见。
另一个想法 - 如果您没有描述寄存器的行为（对于变量来说，这通常归结为在时钟进程中写入它之前读取它），那么不会创建任何寄存器。它只是流程中的组合逻辑，并且很可能与其他事物相结合。也许您可以发布您的整个过程（或更多） - 我们也许可以通过这种方式提供更多帮助。
Has it been optimised away? if the elements of opcode are used for other things, they may have been subsumed into other logic and not visible in their own right anymore.
Another thought - if you haven't described the behaviour of a register (which for a variable usually comes down to reading it before writing to it in a clocked process) then no register will be created. It'll just be combinatorial logic within the process, and very likely to be combined with other things. Maybe you could post your whole process (or a bit more of it) - we might be able to help more that way.