包含取决于目标的文件

发布于 2024-10-03 12:52:40 字数 497 浏览 1 评论 0原文

我有一个 Makefile，其中包含子目录中的 makefile。但是，我想要的是基于所选目标包含这些“子”makefile。

背景是，子 makefile 定义了不同的目标文件，并且根据这些目标文件应该创建目标可执行文件。

假设 sub-makefile1 设置了变量

OBJECTS := foo.o foo1.o

sub-makefile2 设置

OBJECTS := bar.o bar1.o

通用规则是：

lib/%.so: $(OBJECTS)
    link $^ -o $@

目标是（例如）：

foo: lib/foo.so

bar: lib/bar.so

而目标 foo 应该包含 foo makefile，目标 bar 应该包含 bar-makefile。

知道如何处理这种情况吗？

谢谢，基督教

原文

I have a Makefile which includes makefiles from sub-directories.
However, what I want is to include these "sub"-makefiles on base of a selected target.

Background is, that the sub-makefiles define different object files and depending on these object files the target executable should be created.

Assuming sub-makefile1 sets the variable

OBJECTS := foo.o foo1.o

sub-makefile2 sets

OBJECTS := bar.o bar1.o

And the generic rule would be:

lib/%.so: $(OBJECTS)
    link $^ -o $@

The targets are (for example):

foo: lib/foo.so

bar: lib/bar.so

whereas target foo should include the foo makefile, target bar the bar-makefile.

Any idea how to handle this situation?

Thanks,
Christian

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≈。彩虹 2024-10-10 12:52:40

Beta 提到了 $(MAKECMDGOALS)，但没有描述它：

ifeq ($(MAKECMDGOALS),foo)
include sub-makefile1
endif
ifeq ($(MAKECMDGOALS),bar)
include sub-makefile2
endif

# Rest of Makefile follows...

这不是一个好主意，因为它只有在交互调用 make 时才起作用。您可以通过为递归调用 make 的 foo 和 bar 制定规则来解决这个问题：

ifeq ($(MAKECMDGOALS),foo)
include sub-makefile1
foo: # ...
    # Normal commands to build foo
else
foo:
    $(MAKE) lt;
endif

ifeq ($(MAKECMDGOALS),bar)
include sub-makefile2
bar: # ...
    # Normal commands to build bar
else
bar:
    $(MAKE) lt;
endif

Beta has mentioned the $(MAKECMDGOALS), but not described it:

ifeq ($(MAKECMDGOALS),foo)
include sub-makefile1
endif
ifeq ($(MAKECMDGOALS),bar)
include sub-makefile2
endif

# Rest of Makefile follows...

This isn't such a great idea, as it will only work when make is called interactively. You can hack around this by making rules for foo and bar that recursively invoke make:

ifeq ($(MAKECMDGOALS),foo)
include sub-makefile1
foo: # ...
    # Normal commands to build foo
else
foo:
    $(MAKE) lt;
endif

ifeq ($(MAKECMDGOALS),bar)
include sub-makefile2
bar: # ...
    # Normal commands to build bar
else
bar:
    $(MAKE) lt;
endif

回复收藏 0 原文

世界和平 2024-10-10 12:52:40

你所要求的具体事情——条件包含——在Make中是很困难的。这是可以做到的，但并不优雅。

有多种方法可以获得您想要的效果。您可以在 MAKECMDGOALS 上使用条件。您可以让您的 makefile 调用第二个 makefile，并将其传递给要使用的子目录的名称。但是（在不了解更多情况的情况下）我认为这种方式是最简洁的：（

include sub-makefile1
FOO_OBJECTS := $(OBJECTS)

include sub-makefile2
BAR_OBJECTS := $(OBJECTS)

lib/%.so:
    link $^ -o $@

lib/foo.so: $(FOO_OBJECTS)

lib/bar.so: $(BAR_OBJECTS)

foo bar : % : lib/%.so

您可以巧妙地使用诸如 foo_OBJECTS 之类的变量名称来节省一两行，但我建议不要这样做。）

The specific thing you're asking for -- conditional inclusion -- is difficult in Make. It can be done, but it's not elegant.

There are several ways to get the effect you want. You could use a conditional on MAKECMDGOALS. You could could have your makefile invoke a second makefile, and pass it the name of the subdirectory to use. But (without knowing more about the situation) I think this way is the tidiest:

include sub-makefile1
FOO_OBJECTS := $(OBJECTS)

include sub-makefile2
BAR_OBJECTS := $(OBJECTS)

lib/%.so:
    link $^ -o $@

lib/foo.so: $(FOO_OBJECTS)

lib/bar.so: $(BAR_OBJECTS)

foo bar : % : lib/%.so

(You could be clever with variable names like foo_OBJECTS to save a line or two, but I advise against that.)

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