Verilog 中的 BCD 加法器

发布于 2024-10-02 23:30:01 字数 872 浏览 12 评论 0原文

我正在尝试用 Verilog 编写 BCD 加法器，但其中一个模块遇到问题。具体来说，加法器将两个 BCD 数字相加。所以，如果两位数之和小于或等于九，那么它就是正确的。但是，如果它更大，则必须添加 6 的偏移量。到目前为止，这是我的 Verilog 代码：

module DIGITADD(
    input [3:0] IN_A,
    input [3:0] IN_B,
    input CIN,
    output reg COUT,
    output reg [3:0] SUM
);

wire s2, c2;

always @ ( * ) 
begin
 assign {c2, s2} = IN_A + IN_B + CIN;

 if(s2 <= 9 && c2 == 0) begin
  assign {COUT, SUM} = {c2, s2};
 end
 else if({c2, s2} > 9) begin
  assign {COUT, SUM} = {c2, s2 + 6};
 end
end
endmodule

无论如何，当我尝试在 Xilinx 中综合它时，出现以下错误：

ERROR:HDLCompilers:247 - "DIGITADD.v" line 33 Reference to scalarwire 'c2' is not a legal reg或变量左值

ERROR:HDLCompilers:247 - "DIGITADD.v" line 33 对标量线 's2' 的引用不是合法的寄存器或变量左值

ERROR:HDLCompilers:42 - "DIGITADD.v" line 33 程序的左侧非法我尝试更改一些内容

，例如将电线更改为reg，但我仍然无法使其工作。任何帮助表示赞赏。

原文

I am trying to write a BCD Adder in Verilog, but I am having trouble with one of the modules. Specifically, the adder that takes two BCD digits and adds them. So, the idea is if the sum of the two digits is less than or equal to nine, then it is correct. However, if it is greater, then an offset of 6 has to be added. Here is my Verilog code so far:

module DIGITADD(
    input [3:0] IN_A,
    input [3:0] IN_B,
    input CIN,
    output reg COUT,
    output reg [3:0] SUM
);

wire s2, c2;

always @ ( * ) 
begin
 assign {c2, s2} = IN_A + IN_B + CIN;

 if(s2 <= 9 && c2 == 0) begin
  assign {COUT, SUM} = {c2, s2};
 end
 else if({c2, s2} > 9) begin
  assign {COUT, SUM} = {c2, s2 + 6};
 end
end
endmodule

Anyways, when I try to synthesize it in Xilinx, I get the following errors:

ERROR:HDLCompilers:247 - "DIGITADD.v" line 33 Reference to scalar wire 'c2' is not a legal reg or variable lvalue

ERROR:HDLCompilers:247 - "DIGITADD.v" line 33 Reference to scalar wire 's2' is not a legal reg or variable lvalue

ERROR:HDLCompilers:42 - "DIGITADD.v" line 33 Illegal left hand side of procedural assign

I tried changing some things like changing wire to reg, but I still can't get it to work. Any help is appreciated.

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寂寞美少年 2024-10-09 23:30:02

在纯文本中，不要在程序块中使用连续赋值，例如“分配”语句，即“始终”或“初始”。

记住规则，生活就会美好:-)

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冷清清 2024-10-09 23:30:01

好吧，我明白了，正确的代码如下。基本上，请参阅我对我的问题所做的评论，以获取一些需要记住的提示。有趣的是，与我之前遇到的混乱相比，这要简单得多。

module DIGITADD(
    input [3:0] IN_A,
    input [3:0] IN_B,
    input CIN,
    output COUT,
    output [3:0] SUM
    );

reg [4:0] s2;

assign SUM = s2[3:0];
assign COUT = s2[4];

always @ ( * )
begin
    s2 = IN_A + IN_B + CIN;
    if (s2 > 9)
    begin
        s2 = s2 + 6;
    end
end
endmodule

Okay, I figured it out, the correct code is below. Basically, see the comment I made on my question for some tips to remember. Its funny how much simpler this is compared to the mess I had earlier.

module DIGITADD(
    input [3:0] IN_A,
    input [3:0] IN_B,
    input CIN,
    output COUT,
    output [3:0] SUM
    );

reg [4:0] s2;

assign SUM = s2[3:0];
assign COUT = s2[4];

always @ ( * )
begin
    s2 = IN_A + IN_B + CIN;
    if (s2 > 9)
    begin
        s2 = s2 + 6;
    end
end
endmodule

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