Nehalem 内存架构地址映射
给定具有 12GB RAM (6x2GB) 的 2 处理器 Nehalem Xeon 服务器，内存地址如何映射到物理内存模块？
我可以想象，在具有 3 个相同内存模块的单个处理器 Nehalem 上，地址空间将在模块上进行条带化，以提供更好的内存带宽。但是什么样的条纹尺寸呢？第二个处理器（+内存）如何改变这种情况？
Given a 2 processor Nehalem Xeon server with 12GB of RAM (6x2GB), how are memory addresses mapped onto the physical memory modules?
I would imagine that on a single processor Nehalem with 3 identical memory modules, the address space would be striped over the modules to give better memory bandwidth. But with what kind of stripe size? And how does the second processor (+memory) change that picture?
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英特尔对此不是很清楚，你必须深入研究他们的核心技术文档才能找出所有细节。这是我的理解。每个处理器都有一个集成的内存控制器。一些 Nehalems 具有三通道控制器，一些具有双通道控制器。每个内存模块都分配给其中一个处理器。三通道意味着访问在三组模块之间交错，双通道 = 两组。
特定的交错模式在某种程度上是可配置的，但是考虑到它们的设计，最终几乎不可避免地会得到 64 到 256 字节的条带。
如果其中一个处理器想要访问连接到其他处理器的 IMC 的内存，则该访问会经过这两个处理器，并会产生额外的延迟。
Intel is not very clear on that, you have to dig into their hardcore technical documentation to find out all the details. Here's my understanding. Each processor has an integrated memory controller. Some Nehalems have triple-channel controllers, some have dual-channel controllers. Each memory module is assigned to one of the processors. Triple channel means that accesses are interleaved across three banks of modules, dual channel = two banks.
The specific interleaving pattern is configurable to some extent, but, given their design, it's almost inevitable that you'll end up with 64 to 256 byte stripes.
If one of the processors wants to access memory that's attached to the IMC of some other processor, the access goes through both processor and incurs additional latency.