保留端口宽度
我试图在其他设计中重复使用网表，但没有成功。
我有一个转换为网表的组件：
entity c is
port (... sel : in std_logic_vector(31 downto 0); ... );
在设计中我仅使用 sel(4 downto 0)。 综合工具注意到这种行为并发出警告：
'警告：Xst：647 - 输入 sel<31:5>从未使用过..
我正在生成具有以下属性的网表：
- keep hierarchy = true
- add I/O buffers = off
每当我想将此网表实例化为其他电路中的黑盒模块时，我都会收到错误：
错误：NgdBuild:76 - 无法合并到块中，因为在文件中找不到块上的一个或多个引脚，包括引脚“sel<31>”。
如何保留 sel 的大小？ 我应该提到 sel 需要是 32 位宽度，因为它连接到总线。
I am trying to re-use netlists in other designs without the success.
I have a component which is translated to the netlist:
entity c is
port (... sel : in std_logic_vector(31 downto 0); ... );
In the design I am using just sel(4 downto 0).
The synthesis tools notices this behaviour and gives a warning:
'WARNING:Xst:647 - Input sel<31:5> is never used ..
I am generating netlist with properties:
- keep hierarchy = true
- add I/O buffers = off
Whenever I want to instantiate this netlist as an black-box module in other circuit I got an error:
ERROR:NgdBuild:76 - cannot be merged into block because one or more pins on the block, including pin "sel<31>", were not found in the file.
How can I preserve the size of sel?
I should mention that the sel needs to be 32bits width since it's connected to the bus.
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您可以尝试将未使用的输入端口驱动为零。
You could try driving the unused input ports to zero.
您可以直接使用该组件而不是作为预先合成的黑盒吗？
您可以通过在端口上放置 KEEP 属性（请参阅合成工具手册）来使事情正常工作。我只在信号上尝试过这个，但它可能有效。
这类任务通常被描述为合成器的“推绳子”，因为让它不达到预期的速度是非常痛苦的（然后在下一个版本的工具中，您需要不同的属性:)
Can you use the component directly instead of as a pre-synthesised black-box?
You may get things to work by putting a KEEP attribute (see your synth tools manual) on the port. I've only ever tried this on signals, but it may work.
This sort of task is often described as "pushing on the rope" of the synthesiser, as it's such a pain to get it to not be as celever as it wants to be (and then in the next release of tools you need a different attribute :)