This may be the last open source computing stack to be conquer, We already have GNU/Linux, GCC, and perhaps some open source CPU's. But not a complete chip design flow. What you refer is what is known as Place and Route (P&R) in the Electronic Design Industry (EDA) jargon. As far as I know there is not a competitive VLSI flow in the open source community, the investment needed for the development of a complete place and route solution is very big in order of millions of dollars, example of this commercial tools are: Design Compiler, Encounter from Cadence, IC compiler from Synopsis among others. Some of the algorithms for P&R have origin in academia, you may find some code here and there, but not a complete solution.
You can find SPICE, a circuit simulator that foundries and CAD companies use to generate their cell libraries http://en.wikipedia.org/wiki/SPICE
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通常的步骤是：
Verilog -> [编译器]->门级网表-> [地点&路线工具】-> GDSII
您还需要一个开源单元库。快速进行网络搜索，找到地点和地点。可能会出现路线工具。
Usually the steps are:
Verilog -> [Compiler] -> Gate-level netlist -> [Place & Route tool] -> GDSII
You'd need an open-source cell library too. Do a quick interweb search for that, and a place & route tool may show up.
这可能是最后一个要征服的开源计算堆栈，我们已经有了 GNU/Linux、GCC，也许还有一些开源 CPU。但并不是完整的芯片设计流程。您指的是电子设计行业 (EDA) 术语中的布局布线 (P&R)。据我所知，开源社区中还没有具有竞争力的VLSI流程，开发一个完整的布局布线解决方案所需的投资非常大，达到数百万美元，这种商业工具的例子有：Design Compiler 、来自 Cadence 的 Encounter、来自 Synopsis 的 IC 编译器等。 P&R 的一些算法起源于学术界，您可能会到处找到一些代码，但不是完整的解决方案。
您可以找到 SPICE，这是一种电路模拟器，铸造厂和 CAD 公司用它来生成其单元库 http://en。 wikipedia.org/wiki/SPICE
这些是学术和开源标准单元库的一些链接，
http://www.vlsitechnology.org/
http://www.vtvt.ece.vt.edu/vlsidesign/cell.php
但我不确定它们是否可以用于实际生产。但肯定是 EDA 工具流程中的首要组成部分之一。
UCSD 的 Andrew Kahng 教授是 UCSD 的 VLSI 研究员，他保留了 VLSI 有用软件列表，此处：http://vlsicad.ucsd.edu/Resources/SoftwareLinks/index.html 但某些 EDA 链接已损坏。伯克利分校的此列表也可能有所帮助：http://embedded.eecs.berkeley.edu/pubs /downloads/
如果您或某人可能找到一些 P&R 开源代码，请告诉我。希望这有帮助。
This may be the last open source computing stack to be conquer, We already have GNU/Linux, GCC, and perhaps some open source CPU's. But not a complete chip design flow. What you refer is what is known as Place and Route (P&R) in the Electronic Design Industry (EDA) jargon. As far as I know there is not a competitive VLSI flow in the open source community, the investment needed for the development of a complete place and route solution is very big in order of millions of dollars, example of this commercial tools are: Design Compiler, Encounter from Cadence, IC compiler from Synopsis among others. Some of the algorithms for P&R have origin in academia, you may find some code here and there, but not a complete solution.
You can find SPICE, a circuit simulator that foundries and CAD companies use to generate their cell libraries http://en.wikipedia.org/wiki/SPICE
These are some links to academic and open source standard cell libraries,
http://www.vlsitechnology.org/
http://www.vtvt.ece.vt.edu/vlsidesign/cell.php
But I'm not sure if they can be used for real production. But certainly is on of the first ingredients in the EDA tool flow.
Prof. Andrew Kahng from UCSD, is a researcher in VLSI at UCSD, he keeps a list of useful list of software for VLSI, here: http://vlsicad.ucsd.edu/Resources/SoftwareLinks/index.html but some of the EDA links are broken. This list from Berkeley may be helpful also: http://embedded.eecs.berkeley.edu/pubs/downloads/
If you or someone may find some P&R open source let me know. Hope this helps.
查看 Fedora 的 FEL 项目：http://spins.fedoraproject.org/fel/#portfolio
用于单元设计编译的实际工具是 http:// www-asim.lip6.fr/recherche/alliance/doc/design-flow/tools.html#boog（仅适用于 VHDL）
Check out Fedora's FEL project: http://spins.fedoraproject.org/fel/#portfolio
Actual tools for cell design compilig are http://www-asim.lip6.fr/recherche/alliance/doc/design-flow/tools.html#boog (for VHDL only)