添加“1”到 VHDL 中的 LOGIC_VECTOR
我正在尝试将“1”添加到 VHDL 中的 N 长度 STD_LOGIC_VECTOR
这是我第一次使用 VHDL，所以我完全不确定如何在不构建全加器的情况下添加这个 1，这似乎有点 。
我们不允许使用比代码中更多的自由程序
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cnt IS
GENERIC (n: natural :=3);
PORT( clk: IN std_logic; -- clock
rst: IN std_logic; -- reset
cntNum: IN std_logic_vector(n-1 DOWNTO 0); -- # of counting cycles
cntOut: OUT std_logic_vector(n-1 DOWNTO 0) -- count result
);
END cnt;
architecture CntBhvArc OF cnt IS
signal counta : std_logic_vector(n-1 DOWNTO 0);
begin
process (clk, rst)
begin
if rst='1' then
counta<="0";
elsif (clk'event) and (clk='0') then
counta<= counta+'1';
end if;
cntOut<=counta;
end process;
END CntBhvArc
另外...任何人都可以为那些编程经验很少的人提供 VHDL 试用版吗？
谢谢
I'm trying to add '1' to an N-Length STD_LOGIC_VECTOR in VHDL
This is the very first time I'm using VHDL so I'm not at all sure how to add this 1 without bulding a Full-Adder which seems kinda of redundent
We are not allowed to use any more liberaries then then one in the code.
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cnt IS
GENERIC (n: natural :=3);
PORT( clk: IN std_logic; -- clock
rst: IN std_logic; -- reset
cntNum: IN std_logic_vector(n-1 DOWNTO 0); -- # of counting cycles
cntOut: OUT std_logic_vector(n-1 DOWNTO 0) -- count result
);
END cnt;
architecture CntBhvArc OF cnt IS
signal counta : std_logic_vector(n-1 DOWNTO 0);
begin
process (clk, rst)
begin
if rst='1' then
counta<="0";
elsif (clk'event) and (clk='0') then
counta<= counta+'1';
end if;
cntOut<=counta;
end process;
END CntBhvArc
Also... can anyone point to a VHDL totrial for someone who has very little experince in programing?
Thanks
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评论（3）
您不应使用库
IEEE.STD_LOGIC_UNSIGNED.ALL该库已弃用（请参阅VHDL 常见问题);请改用 ieee.numeric_std.all 。
You should not use library
IEEE.STD_LOGIC_UNSIGNED.ALLThis library is deprecated (see VHDL FAQ); use
ieee.numeric_std.allinstead.回答你的最后一点 - 不要将其视为编程。 HDL 代表“硬件描述语言”。您正在描述硬件，在编写代码时请始终牢记这一点:)
我还详细写了 关于不使用 STD_LOGIC_UNSIGNED，而是使用 NUMERIC_STD。如果这是家庭作业并且你被教导使用 STD_LOGIC_UNSIGNED，那么我对教育机构感到失望。自从这变得有意义以来已经过去了很多年。
VHDL 是强类型的，因此如果 count 表示一个数字（并且具有类似的名称，最好是:)，请使用
signed或unsigned向量，或整数。除非您创建整数，否则整数不会在模拟中回绕（如果在它们达到最大值时向它们加 1，模拟器将终止）。向量类型可以。有时你想要一种行为，有时又想要另一种行为。最后，我只是注意到这一点：
最好写成：
同样，这种情况已经持续了大约一两年。如果您打算使用下降沿 - 上升沿更常见。
To answer your last point - don't think of it as programming. HDL stands for "hardware description language". You're describing hardware, always keep it in mind when writing your code :)
I've also written at length about not using STD_LOGIC_UNSIGNED, but using NUMERIC_STD instead. If this is homework and you're being taught to use STD_LOGIC_UNSIGNED, then I despair of the educational establishments. It's been years since that made sense.
VHDL is strongly-typed, so if count is representing a number (and with a name like that, it better had be :), use either a
signedorunsignedvector, or aninteger. Integers don't wrap around in simulation unless you make them (if you add 1 to them when they are at their max value, the simulator will terminate). The vector types do. Sometimes you want one behaviour, sometimes the other.Finally, I just noted this:
which is better written as:
again, this has been so for about a decade or two. Were you intending to use the falling edge - rising edge is more usual.
您需要将 std_logic_vector 转换为无符号值，以便可以加一，然后将其转换回来，以便可以将其分配给输出。
这看起来像是一项家庭作业，所以我将让您自己弄清楚如何实施。
You need to cast the std_logic_vector to an unsigned value so you can add one, then cast it back so you can assign it to your output.
This looks like a homework assignment, so I'll leave you to figure out exactly how to do the implementation.