读取 OUT 端口以进行调试

发布于 2024-09-30 18:26:36 字数 756 浏览 0 评论 0原文

我有一个 FIFO,它有一个看起来像这样的接口:

entity fifo is
    port (
    CLK               : IN  std_logic := '0';
    DIN               : IN  std_logic_vector(31 DOWNTO 0);
    ALMOST_EMPTY      : OUT std_logic;
    ALMOST_FULL       : OUT std_logic;
    DOUT              : OUT std_logic_vector(31 DOWNTO 0);
    ...
    WR_ACK            : OUT std_logic
);
end fifo;

这个接口是给定的,我不能改变 iy。出于调试目的,我想查看 FIFO 写入和读取的内容。换句话说,理想情况下我想分配两个调试 FIFO 的输入和输出值,即,

  DBG_FIFO_IN  <= DIN;
  DBG_FIFO_OUT <= DOUT;

出于明显的原因,第二个分配给了我以下错误消息:

[exec] 错误:HDLParsers:1401 - 模式 OUT 的对象 DOUT 无法 阅读。

我想知道是否有任何方法可以将 DOUT 值分配给我的调试符号。接口已经给定了,所以我无法将DOUT设置为输入输出信号。

I have a FIFO which has an interface that looks something like this:

entity fifo is
    port (
    CLK               : IN  std_logic := '0';
    DIN               : IN  std_logic_vector(31 DOWNTO 0);
    ALMOST_EMPTY      : OUT std_logic;
    ALMOST_FULL       : OUT std_logic;
    DOUT              : OUT std_logic_vector(31 DOWNTO 0);
    ...
    WR_ACK            : OUT std_logic
);
end fifo;

This interface is given, and I can't change iy. For debugging purposes, I want to see what is written and read to/from the FIFO. In other words, ideally I would like to assign two debug the in and out values of the FIFO, i.e.,

  DBG_FIFO_IN  <= DIN;
  DBG_FIFO_OUT <= DOUT;

For obvious reasons, the second assignment gives me the following error message:

[exec] ERROR:HDLParsers:1401 - Object DOUT of mode OUT can not be
read.

I am wondering if there is any way how I can assign the DOUT value to my debug symbol. The interface is given, so I can't make DOUT an inout signal.

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评论(3

无畏 2024-10-07 18:26:36

您必须将 fifo 输出分配给您可以读取的本地信号,然后将该信号分配给输出(或并行分配它们):

DBG_FIFO_OUT <= (your logic here);
DOUT         <= DBG_FIFO_OUT;

DBG_FIFO_OUT <= (your logic here);
DOUT         <= (your logic here);

You have to assign the fifo output to a local signal you can read, then assign that signal to the output (or assign them both in parallel):

DBG_FIFO_OUT <= (your logic here);
DOUT         <= DBG_FIFO_OUT;

or

DBG_FIFO_OUT <= (your logic here);
DOUT         <= (your logic here);
虫児飞 2024-10-07 18:26:36

使用 BUFFER 代替 out。然后您就可以在没有查尔斯解决方案中使用的中间信号的情况下进行读取。

Use BUFFER instead of out. Then you can read without the intermediate signal used in Charles' solution.

泪眸﹌ 2024-10-07 18:26:36

对于旧工具,您已经有了很好的答案 - 但如果您使用一些支持 VHDL-2008 的工具,您可以直接读取输出端口。您可能需要使用命令行选项启用此功能。

如果您的工具不支持它,请向供应商抱怨,直到他们支持为止!

You have good answers already for older tools - but if you use some tool which supports VHDL-2008, you are allowed to read output ports directly. You may need to enable this with a command line option.

If your tools don't support it, whinge at the supplier until they do!

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