意外的 TICK 错误

发布于 2024-09-30 11:29:33 字数 867 浏览 0 评论 0原文

我正在尝试编写 VHDL 模块，但 if 语句有问题。这很可能是一个愚蠢的错误，但由于我对 VHDL 很陌生，所以我无法找出问题所在。这是我的代码：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


entity binary_add is
    port( n1 : in std_logic_vector(3 downto 0);
    n2 : in std_logic_vector(3 downto 0);
    segments : out std_logic_vector(7 downto 0);
    bool : out bit;
    o : out std_logic_vector(3 downto 0);
    DNout : out std_logic_vector(3 downto 0));

end binary_add;

architecture Behavioral of binary_add is
begin

process(n1, n2) 
begin

o <= n1 + n2;

if( o = '1010') then 
bool <= '1';
else
bool <= '0';
end if;

end process;

end Behavioral;

我从 if 语句的第一行得到以下答案：

ERROR:HDLParsers:## - "C:/Xilinx/12.3/ISE_DS/ISE/.../binary_add.vhd" Line ##. parse error, unexpected TICK

我做错了什么？

原文

I am trying to write a VHDL module but I have a problem with the if statement. Most probably it is a silly mistake, but since I am very new to VHDL, I could not figure out the problem. Here is my code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


entity binary_add is
    port( n1 : in std_logic_vector(3 downto 0);
    n2 : in std_logic_vector(3 downto 0);
    segments : out std_logic_vector(7 downto 0);
    bool : out bit;
    o : out std_logic_vector(3 downto 0);
    DNout : out std_logic_vector(3 downto 0));

end binary_add;

architecture Behavioral of binary_add is
begin

process(n1, n2) 
begin

o <= n1 + n2;

if( o = '1010') then 
bool <= '1';
else
bool <= '0';
end if;

end process;

end Behavioral;

And I get the following answer from the first line of if statement:

ERROR:HDLParsers:## - "C:/Xilinx/12.3/ISE_DS/ISE/.../binary_add.vhd" Line ##. parse error, unexpected TICK

What am I doing wrong?

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谢绝鈎搭 2024-10-07 11:29:33

“1010”应该是“1010”（双引号）。单引号用于字符文字（单个字符）。

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寄居者 2024-10-07 11:29:33

所以你已经按照马克的回答修复了第一个错误。

第二个错误是您无法利用输出的值。

if output = "0101";    -- illegal

some_signal <= output; -- illegal

为了解决这个问题，您需要创建一个内部信号（例如求和）。然后，您可以使用内部信号，并将其分配给外部信号。

architecture Behavioral of binary_add is

signal sum : std_logic_vector(3 downto 0);

begin

process(n1, n2, sum) 
begin

sum <= n1 + n2;

if( sum = '1010') then 
bool <= '1';
else
bool <= '0';
end if;

end process;

o <= sum;

end Behavioral;

So you have fixed the first error as per Mark's answer.

The second error is that you can not make use of the value of an output.

if output = "0101";    -- illegal

some_signal <= output; -- illegal

To solve this you need to create an internal signal (say sum). You then use the internal signal, and assign it to the external signal.

architecture Behavioral of binary_add is

signal sum : std_logic_vector(3 downto 0);

begin

process(n1, n2, sum) 
begin

sum <= n1 + n2;

if( sum = '1010') then 
bool <= '1';
else
bool <= '0';
end if;

end process;

o <= sum;

end Behavioral;

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