来自 stratch 的多周期数据路径写入中的乘法
我想知道处理器如何从一开始即从指令读取 -> 开始在多周期数据路径中进行乘法运算。解码指令->读取寄存器文件等。
换句话说，我想知道，考虑到单独实现的 Booth 乘法算法（给出了电路），您将如何扩展多周期数据路径以使用最少的资源支持乘法指令。
你也能说出除法吗？
I wanted to know how the processor does multiplication in a multi-cycle data-path right from the beginning i.e from Instruction Reading -> decoding the instruction-> reading register files etc.
In other word I wanted to know that given the booth's algorithm for multiplication implemented separately (a circuit is given) how will you extend the multi-cycle data-path to support multiply instruction using minimum resources.
Can you tell for division also?
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另一个很好的链接是开源 OpenFire 微处理器核心，MicroBlaze 的变体/模拟（基于 DLX）：
http://opencores.org/websvn,listing?repname=openfire_core&path=%2Fopenfire_core%2Ftrunk%2Fopenfire_top_syn%2Fhdl %2Fverilog%2F#path_openfire_core_trunk_openfire_top_syn_hdl_verilog_
ALU 和乘法器单元的部分数据路径位于
openfire_primitives.v文件中。DLX 数据路径手册，对管道停顿和气泡有很好的解释，
http://www.cs.iastate.edu/~prabhu/Tutorial/PIPELINE/hazards.html
并且有有关多周期操作 (DLX) 的信息
http://www.cs.iastate.edu/~prabhu/Tutorial/PIPELINE/ multicycle.html
因此，可以留在管道中（需要更多滴答）的操作将向管道插入停顿（或气泡）。您可以将其视为停止除 EX 之外的管道的所有阶段，EX 会针对多个任务执行 Long 操作。
开源 Verilog 的另一个 Mul/Div 单元在这里：
http://opencores. org/websvn,filedetails?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1200%2Frtl%2Fverilog%2For1200_mult_mac.v
Another good link is the opensource OpenFire microprocessor core, variant/analog of MicroBlaze (which is based on DLX) here:
http://opencores.org/websvn,listing?repname=openfire_core&path=%2Fopenfire_core%2Ftrunk%2Fopenfire_top_syn%2Fhdl%2Fverilog%2F#path_openfire_core_trunk_openfire_top_syn_hdl_verilog_
Part of datapath for ALU and Multiplier unit is in
openfire_primitives.vfile.Manual of DLX datapath with good explanation of pipeline stalls and bubbles is
http://www.cs.iastate.edu/~prabhu/Tutorial/PIPELINE/hazards.html
And there is info on mulitcycle ops (DLX)
http://www.cs.iastate.edu/~prabhu/Tutorial/PIPELINE/multicycle.html
So, operation which can stay in pipeline (need more ticks) will insert stalls (or bubble) to pipeline. You can think about this as stopping all stages of pipeline besides EX, which do a Long operation for several tisks.
Another Mul/Div unit of opensource Verilog is here:
http://opencores.org/websvn,filedetails?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1200%2Frtl%2Fverilog%2For1200_mult_mac.v
对于简单的 cpu 乘法，将在 CPU 管道的 EX 阶段进行。因此，获取指令，对其进行解码，向 RegisterFile 请求输入操作数，在 ALU 上执行实际的乘法。
根据 ALU 变体，乘法可能需要 1 个 CPU 周期或更多（在每个 cpu 周期上存储部分和，然后它将在 CPU 管道的 EX0、EX1、EX2 等阶段）。慢速 ALU 可以流水线化，因此它将在 N 个时钟周期内给出第一个操作的结果，并在每个 M 周期启动不同的操作
您可以在页面上获得乘法器的各种硬件变体
http://www.aoki.ecei.tohoku.ac.jp /arith/mg/algorithm.html
For the simple cpu multiplication will be on the phase EX of CPU pipeline. So Fetch instruction, Decode it, Ask RegisterFile for input operands, Execute actual multiplication on ALU.
Depends on ALU variant, multiplication can take 1 CPU cycle or more (with storing of partial sums on each cpu cycle, then it will be on EX0, EX1, EX2 etc stages of CPU pipeline). Slow ALUs can be pipelined, so It will give result of first operation in N ticks, and start different operations each M
The various hardware variants of multipliers you can get on the page
http://www.aoki.ecei.tohoku.ac.jp/arith/mg/algorithm.html