将 Altera M9K 的内容重置为 0（上电值）
你好，
我正在开发 Stratix III FPGA，它包含 M9K 块存储器，其内容在上电时可以方便地初始化为零。这非常适合我的应用。
有没有一种方法可以将内容重置为零，而无需对 FPGA 进行电源循环/重新刷新等操作？ megawizard插件管理器中似乎没有这样的选项，我想避免浪费一堆逻辑，这些逻辑只是依次向每个地址写入零......
我环顾四周，没有提到这样的机制，但我想我会问以防万一有人知道一个方便的技巧:]顺便说一句，我正在使用 VHDL，但我应该能够翻译任何 Verilog。
数据表（不包含答案！）：http://www.altera.com /literature/hb/stx3/stx3_siii51004.pdf
提前致谢，
- Thomas
PS：这是我在这里发表的第一篇文章，所以如果我违反了任何礼仪，请告诉我:)
Good day,
I am working on a Stratix III FPGA which contains M9K block memories, the contents of which are conveniently initialised to zero on power-on. This suits my application very well.
Is there a way to reset the contents back to zero without power-cycling/reflashing/etc the FPGA? There seems to be no such option in the megawizard plugin manager, and I would like to avoid wasting a bunch of logic which just goes and sequentially writes zero to every address...
I have looked around and there is no reference to such a mechanism, but I thought I'd ask just in case someone knew a handy trick :] By the way I'm working in VHDL but I should be able to translate any Verilog.
Datasheet (does not contain the answer!) : http://www.altera.com/literature/hb/stx3/stx3_siii51004.pdf
Thanks in advance,
- Thomas
PS: This be my first post here, so if I've violated any etiquette please let me know :)
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抱歉，传统的方法是：
在解决方案空间的古怪一端，我想如果您已经在 FPGA 中或外部拥有微控制器，我想您也可以将某些东西连接到 JTAG 端口 - 您可能能够覆盖 RAM内容也是如此。
Sorry, the conventional ways to do that are:
At the wackier end of the solution space, I guess you could also wire something up to the JTAG port if you already have a microcontroller either in the FPGA or outside - you might be able to overwrite the RAM contents that way too.