进程内的冗余循环（VHDL）？

发布于 2024-09-18 06:04:16 字数 608 浏览 3 评论 0原文

我正在上一门大学课程，学习使用 VHDL 进行数字设计，前几天我在书中阅读了一些内容，其中我遇到了以下代码：

architecture abstract of computer_system is
    ...

    cpu : process is
        variable instr_reg : word;
        variable PC : natural;
        ...
    begin
        loop
            address <= PC;
            mem_read <= '1';
            wait until mem_ready;
            ...
        end loop;
    end process cpu;
end architecture abstract;

现在，正如我所理解的，一旦一个进程到达最后一个语句，它将返回并执行第一条语句（当然，前提是最后一条语句不是 wait）。而loop ... end Loop;的目的是无限重复中间代码。那么在这种情况下这不会使循环变得多余吗？它是否添加了流程尚未表现出的任何额外行为？

原文

I'm taking a university course to learn digital design using VHDL, and was doing some reading in the book the other day where I came across the following piece of code:

architecture abstract of computer_system is
    ...

    cpu : process is
        variable instr_reg : word;
        variable PC : natural;
        ...
    begin
        loop
            address <= PC;
            mem_read <= '1';
            wait until mem_ready;
            ...
        end loop;
    end process cpu;
end architecture abstract;

Now, as I've understood it, once a process reaches its last statement, it will go back and execute the first statement (provided that the last statement wasn't a wait, of course). And the purpose of loop ... end loop; is to repeat the intermediate code indefinitely. So doesn't that make the loop redundant in this case? Does it add any extra behaviour that isn't already exhibited by the process?

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