上交所挤满的流通股上翻转标志
我正在寻找最有效的方法来翻转 SSE 寄存器中所有四个浮点数的符号。
我没有在英特尔架构软件开发手册中找到执行此操作的内在函数。以下是我已经尝试过的事情。
对于每种情况,我都将代码循环 100 亿次,并得到了显示的挂起时间。我试图至少匹配 4 秒,它需要我的非 SIMD 方法,该方法仅使用一元减运算符。
[48秒]_mm_sub_ps( _mm_setzero_ps(), vec );
[32 秒]_mm_mul_ps( _mm_set1_ps( -1.0f ), vec );
[9 秒]
union NegativeMask { int intRep; float fltRep; } negMask; negMask.intRep = 0x80000000; _mm_xor_ps( _mm_set1_ps( negMask.fltRep ), vec );
编译器是带 -O3 的 gcc 4.2。 CPU 是 Intel Core 2 Duo。
I'm looking for the most efficient method of flipping the sign on all four floats packed in an SSE register.
I have not found an intrinsic for doing this in the Intel Architecture software dev manual. Below are the things I've already tried.
For each case I looped over the code 10 billion times and got the wall-time indicated. I'm trying to at least match 4 seconds it takes my non-SIMD approach, which is using just the unary minus operator.
[48 sec]_mm_sub_ps( _mm_setzero_ps(), vec );
[32 sec]_mm_mul_ps( _mm_set1_ps( -1.0f ), vec );
[9 sec]
union NegativeMask { int intRep; float fltRep; } negMask; negMask.intRep = 0x80000000; _mm_xor_ps( _mm_set1_ps( negMask.fltRep ), vec );
The compiler is gcc 4.2 with -O3. The CPU is an Intel Core 2 Duo.
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这个联合并不是真正需要的,最重要的是(可读性、速度和可移植性):
That union is not really needed, best of all worlds (readability, speed and portability):
只是为了通过有关这些内置向量的 gcc 文档来完成您自己的答案:
尽可能始终坚持这些可能是一个好主意。 gcc 很有可能始终为 SSE 提供最有效的代码。
对于您的编译器选项,请添加一些更具体到您的架构的内容,例如
-march=native
在大多数情况下都可以。Just to complete your own answer by the gcc documentation about these builtin vectors:
It is probably a good idea to always stick to these when possible. With very high chances gcc will always provide the most efficient code for this SSE stuff.
For your compiler options, add something more specific to your architecture, something like
-march=native
will do in most cases.关于编码的人生课程,直到凌晨 3 点......
我从未尝试过在我的打包向量上使用一元减号。实际上,它的编译性能与非 SIMD 方法完全相同。
A life lesson about coding till 3am in the morning.....
I never tried just using the unary minus on my packed vector. That actually compiles and has the exact same performance as the non-SIMD approach.