扩展 Sugiyama 的布局算法以用于具有多个输入的块
我正在尝试使用 Sugiyama 的有向图布局算法来生成漂亮的 verilog 电路图。我遇到的问题是布局算法假设每个块（或顶点）只有一个输入或输出边缘。但实际电路可以具有具有多个输入和输出连接的模块，理想情况下这些连接保持固定顺序。
我正在考虑为每个输入添加额外的顶点，但以某种方式将连接到一个块的所有顶点视为一个单元 - 在Python中，类似于 [ [a.in], [b.in], [c.in1 , c.in2] ] 其中 c 是具有 2 个输入的块。在构建层之间的连接矩阵时，该列表将被展平。
我走在正确的轨道上吗？有没有更简单的方法来做到这一点？您能给我指出任何可以帮助我扩展 Sugiyama 算法来处理此类块的资源吗？
I'm messing around with using Sugiyama's directed graph layout algorithm to generate nice plots of verilog circuits. The problem I'm having is that the layout algorithm assumes that each block (or vertex) has only one input or output edge. But real circuits can have blocks that have multiple input and output connections, which ideally remain in a fixed order.
I was thinking of adding extra vertexes for each input, but somehow treating all the vertices connected to one block as a unit - in Python, something like [ [a.in], [b.in], [c.in1, c.in2] ] where c is a block with 2 inputs. The list would be flattened when building the connection matrices between layers.
Am I on the right track? Is there an easier way to do this? Can you point me to any resources which will help me extend Sugiyama's algorithm to deal with such blocks?
如果你对这篇内容有疑问，欢迎到本站社区发帖提问 参与讨论，获取更多帮助，或者扫码二维码加入 Web 技术交流群。
绑定邮箱获取回复消息
由于您还没有绑定你的真实邮箱，如果其他用户或者作者回复了您的评论，将不能在第一时间通知您！
发布评论