FPGA布局与路线
对于FPGA编程，是否可以自己写地方&路线惯例？ [重点不是我的会更好；而是我的更好。关键是我是否有这样做的自由]——或者这个地方和地方是否有这样做的自由。将阶段输出路由到未记录的位文件中，本质上迫使我使用专有工具？
谢谢！
For programming FPGAS, is it possible to write my own place & route routines? [The point is not that mine would be better; the point is whether I have the freedom to do so] -- or does the place & route stage output into undocumented bitfiles, essengially forcing me to use proprietary tools?
Thanks!
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过去在 comp.arch.fpga 上对此进行过一些讨论。结论通常是，除非您想引起 FPGA 公司的强烈法律诉讼，否则您可能不想做这样的事情。位文件格式是 FPGA 公司严密保守的秘密，您可能必须了解该文件格式才能完成您想做的事情。这意味着您需要对格式进行逆向工程，并且（如果您以任何方式公开您的工具）会在短时间内让您提起诉讼。
我要补充的是，可能存在中间文件，并且您可能不会读取或写入位文件本身来执行您想做的事情，但这些中间文件往往也没有记录。阅读您的 FPGA 综合工具（例如 Xilinx 的 ISE）的 EULA - 严格禁止任何类型的逆向工程。似乎我们在这个领域拥有开源替代品的唯一方法就是开源 FPGA 架构的出现。
There's been some discussion of this on comp.arch.fpga in the past. The conclusion is generally that unless you want to attract intense legal action from the FPGA companies then you probably don't want to do something like this. bitfile formats are closely guarded secrets of the FPGA companies and you would likely have to understand the file format in order to do what you want to do. That implies that you would need to reverse engineer the format and that (if you made your tool public in any way) would get you a lawsuit in short order.
I will add that there probably are intermediate files and that you likely wouldn't read or write the bitfile itself to do what you want to do, but those intermediate files tend to be undocumented as well. Read the EULA for your FPGA synthesis tool (ISE from Xilinx, for example) - any kind of reverse engineering is strictly forbidden. It seems that the only way we'll ever have open source alternatives in this space is for an open source FPGA architecture to emerge.
我同意 annccodeal 的观点，但放大一点，在 Xilinx 上，可能有几种方法可以做到这一点。 XDL 文件格式允许（或用于允许）显式布局和布线。此外，应该可以编写 FPGA 编辑器脚本来实现自定义路由。
至于布局，有丰富的基础设施来约束逻辑到基元的技术映射并控制这些基元的布局。例如，LUT_MAP 约束可以控制技术映射，LOC 和 RLOC 约束可以确定布局。在实践中，这些使得经验丰富的设计人员能够很好地控制设计的实现方式，而不需要他们重复几个世纪的软件开发来直接生成比特流。
您可能还会对当前最先进的 FPGA CAD 研究软件感兴趣，例如 VPR。在我看来，这些都面临着跟上供应商自己的工具的挑战，这些工具必须应对具有可拆分 6-LUT、DSP 块等的现代异构 FPGA。
快乐黑客。
I agree with annccodeal, but to amplify a little bit, on Xilinx, there may be a few ways to do this. The XDL file format allows (or used to allow) explicit placement and routing. In addition, it should be possible to script the FPGA Editor to implement custom routing.
As regards placement, there is a rich infrastructure to constrain technology mapping of logic to primitives and to control placement of those primitives. For example LUT_MAP constraints can control technology mapping and LOC and RLOC constraints can determine placement. In practice, these allow the experienced designer great control over how a design is implemented without requiring them to duplicate man-centuries of software development to generate a bitstream directly.
You may also find interesting the current state of the art FPGA CAD research software such VPR. In my opinion these are challenged to keep up with vendor's own tools that must cope with modern heterogeneous FPGAs with splittable 6-LUTs, DSP blocks, etc.
Happy hacking.