大规模VHDL模块化技术
我正在考虑用 VHDL 实现 16 位 CPU。 一个简单的CPU。 ADD、MULS、NEG、BitShift、JUMP、相对跳转、BREQ、相对 BREQ，我不知道这些内容> 可能都只适用于 16 位操作数。 我什至可能会减少它并仅使用一个操作数和一个累加器。 有了一些状态寄存器，进位，零，负（除非我使用累加器），
我知道如何从逻辑门设计所有部分，并计划从第一原理构建它们， 因此，对于我的 ALU，我需要“构建”一个加法器，可能是一个进位前瞻、组加法器， 这个加法器本身由几个部分组成，而这些部分本身又由几个部分组成。
不管怎样，我的问题不是CPU设计，也不是VHDL（我或多或少了解这种语言）。 这就是我应该让事情井井有条的方式。 我应该如何使用包， 我应该如何命名我的进程和端口映射？ （我从未见过命名端口映射或进程的好处）
I'm thinking about implimenting a 16 bit CPU in VHDL.
A simplish CPU.
ADD, MULS, NEG, BitShift, JUMP, Relitive Jump, BREQ, Relitive BREQ, i don't know somethign along these lines>
Probably all only working with 16bit operands.
I might even cut it down and use only a single operand and a accumulator.
With Some status regitsters, Carry, Zero, Neg (unless i use a Accumlator),
I know how to design all the parts from logic gates, and plan to build them up from first priciples,
So for my ALU I'll need to 'build' a ADDer, proably a Carry Look ahead, group adder,
this adder it self is make up oa a couple of parts, wich are themselves made up of a couple of parts.
Anyway, my problem is not the CPU design, or the VHDL (i know the language, more or less).
It's how i should keep things organised.
How should I use packages,
How should I name my processes and port maps? (i've never seen the benifit of naming the port maps, or processes)
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无论您做什么，一定要阅读 Jiri Gaisler 关于结构化 VHDL 设计方法的杰作。
http://www.gaisler.com/doc/vhdl2proc.pdf
http://www.gaisler.com/doc/structdes.pdf
你会很高兴你这么做了。
Whatever you do, be sure to read Jiri Gaisler's master work on structured VHDL design method.
http://www.gaisler.com/doc/vhdl2proc.pdf
http://www.gaisler.com/doc/structdes.pdf
You'll be very glad you did.
查看一些现有的示例不会伤害。在您谈论的级别（命名约定等），我在硬件设计方面从未真正与软件设计有太大不同。
顺便说一句，我通常建议不要做自己的加法器之类的事情，除非这是因为家庭作业或类似的事情而需要的东西。使用 FPGA 和（在较小程度上）ASIC，您在设备中拥有一个现有的硬件“库”，因此诸如
A <= B + c如果是 FPGA，通常会使用已内置于设备中的加法器电路；如果是 ASIC，则通常会使用手动优化的硬宏。自己编写需要大量的额外工作，而且几乎总是会产生更糟糕的结果。如果是 ASIC，情况会更糟一些；对于 FPGA，情况通常会更糟。
编辑：我还应该注意到，简单的 CPU 并不真正符合大规模设计的条件，至少在我看来是这样。也许是因为我的软件背景，但我一直发现 CPU 设计相当简单。仅举一个例子，有一次我做了一个 DRAM 控制器，对我来说似乎还有很多工作要做。我不记得像源代码行数这样的东西，但根据记忆，我会说它更大（可能是 2 倍之类的）。当然，这也取决于您选择的 CPU 的简单程度......
Looking at some existing examples wouldn't hurt. At the level you're talking about (naming conventions and such) I've never really done much different in hardware design than in software.
As an aside, I'd generally advise against doing things like your own adders and such, unless it's something that's required because it's homework, or something like that. With FPGA's and (to a slightly lesser extent) ASICs, you have an existing "library" of hardware in the device, so some thing like
A <= B + cwill typically use an adder circuit that's already built into the device in the case of an FPGA or a hand-optimized hard macro in the case of an ASIC.Writing your own will take a fair amount of extra work, and it'll almost always produce a worse result. In the case of an ASIC, it'll be a little worse; in the case of an FPGA, it'll usually be quite a bit worse.
Edit: I should also note that a simple CPU doesn't really qualify as a large-scale design, at least IMO. Maybe it's due to my background in software, but I've always found CPU design fairly straightforward. Just for one example, the one time I did a DRAM controller, it seemed like a lot more work to me. I don't recall anything like source code line counts, but based on memory, I'd say it was larger (probably by something like 2x). Of course, it'll depend on exactly how simple of a CPU you decide on too...