8086 多重处理有什么标准吗？
当我制作 8086 模拟器时，我注意到有 LOCK 前缀用于多处理器环境中的同步。然而这是我所知道的 x86 架构的唯一多任务处理。涉及到 APIC 的使用，而 APIC 直到 Pentium 或 486 才出现。
8086 多任务处理是否有任何类型的标准，或者是由某些制造商对指令集和/或特殊端口的特定扩展完成的？
按照标准，我的意思是：如果两个处理器都使用相同的内存，如何将它们分开？如果没有某种方法让每个处理器执行不同的代码，这是不可能的。 （或仅在一个处理器上引起中断）
Back when I made an 8086 emulator I noticed that there was the LOCK prefix intended for synchonization in a multiprocessor environment. Yet the only multitasking I know of for the x86 arch. involves use of the APIC which didn't come around until either the Pentiums or 486s.
Was there any kind of standard for 8086 multitasking or was it done by some manufacturer specific extensions to the instruction set and/or special ports?
By standard, I mean things like: How do you separate the 2 processors if they both use the same memory? This is impossible without some kind of way to make each processor execute a different piece of code. (or cause an interrupt on only one processor)
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如果他们通过英特尔的 MULTIBUS 访问相同的内存，那么 LOCK 前缀就会导致这种序列化。
如果内存本地安装在一个处理器的电路板上，则 LOCK 前缀不会阻止其他处理器通过 MULTIBUS 进入并同时访问该板的内存。在这种配置中，程序员必须玩其他游戏来锁定总线（并在完成内存操作后解锁总线）。
If they accessed the same memory via Intel's MULTIBUS then the LOCK prefix caused exactly that kind of serialization.
If the memory was installed locally on one processor's circuit board then the LOCK prefix would not prevent other processors from coming in over the MULTIBUS and accessing this board's memory at the same time. In this configuration the programmer would have to play other games to lock the bus (and unlock the bus after finishing the memory operation).
好吧，我不是这方面的专家，但我会尝试。
需要记住的一点是：不要认为“PC”或“PC 架构”。回到过去，在 IBM PC 出现之前（更不用说标准的个人计算机设计），英特尔并不生产 PC CPU；而是生产 PC CPU。它正在制造微处理器。对于可以与 8086 结合使用的硬件组件没有确切的期望。您可以使用它来制造硬件微控制器、电子计算器、航空电子设备，以及——哦，当然——家用计算机。
LOCK前缀的作用（据我所知，距离我上次查看英特尔程序员手册已经过去了近 15 年）是在指令执行期间向微处理器的“总线锁定”线发出信号。这是否有任何影响，取决于您连接到该线上的内容！通常情况下，是的，该线被插入到电路中，以防止其他组件使用任何数据线；这就是巴士成为“巴士”的原因（但我不太熟悉细节）。令人困惑的一个原因是多任务处理与多处理器不同（或者我们应该将其称为多组件？）。我不知道有人试图将两个 8086 插入同一总线的 PC 组装在一起，但 CPU 并不是唯一连接到总线的东西，即使在 PC 架构中也是如此。例如，8086中运行的软件在访问与外部输入设备共享的一块内存时可能需要锁定总线，因此外部输入设备无法在8086读取它的同时对其进行写入。我想即使是老式 PC BIOS 也有相当多的情况发生。
当今的多处理器架构仍然依赖于 LOCK 前缀来协调不同处理器之间的关系。但这并不是它存在的主要原因，也不是它的唯一用途。
Well, I'm not an expert here, but I'll try.
Something to keep in mind: Don't think "PC" or "PC architecture". Back in the day, before the IBM PC existed (let alone a standard personal computer design), Intel wasn't making PC CPU's; it was making micro-processors. There were no exact expectations on what hardware components you could combine with an 8086. You could use it to make hardware microcontrollers, electronic calculators, avionics, and -- oh, sure -- home computers.
What the
LOCKprefix does (as I remember, it's been nearly 15 years since I last looked at the Intel programmer manuals) is signaling the "bus lock" line of the microprocessor for the duration of the instruction execution. Whether that had any effect, depended on what you wired to that line! Normally, yes, the line was plugged to circuitry that would prevent other components from using any of the data lines; that's what makes a bus a "bus" (but I'm not very familiar with the details).A source of confusion is that multitasking is not the same as multiprocessor (or should we call it multicomponent?). I don't know that anybody tried to put together a PC with two 8086's plugged to the same bus, but CPUs are not the only thing wired to the bus, even in the PC architecture. For example, The software running in the 8086 might need to lock the bus when accessing a piece of memory shared with an external input device, so the external input device could not write to it at the same time the 8086 was reading it. I imagine even an old fashion PC BIOS has a fair share of this going on.
Today's multiprocessor architectures still rely on the
LOCKprefix to coordinate between different processors; but that was not the primary reason why it exists and it's not its only use.现代 Intel CPU 的内存访问：
CPU 通过 FSB（前端总线）连接到北桥（内存控制器集线器） 。北桥共享对内存总线、AGP 和 PCI（图形）以及用于与南桥连接的内部总线的访问。检查图：
和 CPU 控制通过多个硬件引脚进行 FSB 访问：
FSB 的所有权。
请求巴士。
数据交易。
编辑 I：
对于 8086 CPU 系统：
当CPU必须与其他外设共享数据总线和地址总线时，可以使用DMA 8237控制器解决这个问题
在多 CPU 8086 系统中，使用 Intel Multibus IEEE 796 总线标准。
检查多总线说明。
编辑 II：
8086 多 CPU 系统具有全局（系统）内存，并且该内存通过多总线共享。
因此系统中的任何CPU都有自己的代码和数据存储器，并通过多总线访问全局存储器。
当CPU仲裁和传输总线控制时，这里采用的是串行和并行优先方案。然而，有很多硬件引脚来控制总线访问。总线锁定由#LOCK 引脚实现，所有其他CPU 的#BUSY 引脚将在此时处于高电平。
Memory access at modern Intel CPUs:
CPU is conectet via FSB (Front-side bus) to NorthBridge (memory controller hub). The NorthBridge share access to the memory bus, AGP and PCI (graphic) and Internal bus for connection with SouthBridge. Check diagram:
And CPU control FSB access via several hardware pins:
ownership of FSB.
request the bus.
data transaction.
EDIT I:
For 8086 CPU sistem:
When CPU must share data bus and address bus with other peripheral than this is solved with DMA 8237 controller
In multiple CPU 8086 sistems the Intel Multibus IEEE 796 bus standard is in use.
Check Multibus description.
EDIT II:
8086 Multi-CPU systems have global (system) memory and this memory is shared via multibus.
So any CPU in system has own code and data memory and access to global memory via multibus.
Wheh CPU arbitrating and transferring bus control than are here serial and parallel priority scheme. However ther are a lot of hardware pins to controll bus access. Bus lock is made by #LOCK pin and all other CPUs will have #BUSY pin for that time on high level.