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二进制数比较

发布于 2024-09-01 04:48:49 字数 166 浏览 5 评论 0原文

如果我有一个 32 位二进制补码数字，并且我想知道知道两个数字相等的最简单方法是什么...知道这个的最快按位运算符是什么？我知道对两个数字进行异或并检查结果是否为零效果很好......还有其他的吗？

如果一个数字大于0怎么办？我可以检查第 31 位，看看它是否大于或等于 0..但是 bgtz 怎么样？

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ㄖ落Θ余辉 2024-09-08 04:48:49

与您的评论相反，“==”是 Verilog 的一部分，除非我今晚的记忆力比平常差很多，否则它应该可以很好地综合。例如，您可以编写如下内容：

// warning: untested, incomplete and utterly useless in any case.
// It's been a while since I wrote much Verilog, so my syntax is probably a bit off
// anyway (might well be more like VHDL than it should be).
//
module add_when_equal(clock, a, b, x, y, z);
input clock;
input [31:0] a, b, x, y;
output [31:0] z;
reg [31:0] a, b, x, y, z;

always begin: main
   @(posedge clock);
   if (a == b)
       z <= x + y;
end
endmodule;

Verilog 还支持您通常期望的其他比较运算符（!=、<= 等）。合成器相当“智能”，因此像 x != 0 这样的东西通常会合成到 N 输入 OR 门而不是比较器。

Contrary to your comments, '==' is part of Verilog, and unless my memory is a lot worse than usual tonight, it should synthesize just fine. Just for example, you could write something like:

// warning: untested, incomplete and utterly useless in any case.
// It's been a while since I wrote much Verilog, so my syntax is probably a bit off
// anyway (might well be more like VHDL than it should be).
//
module add_when_equal(clock, a, b, x, y, z);
input clock;
input [31:0] a, b, x, y;
output [31:0] z;
reg [31:0] a, b, x, y, z;

always begin: main
   @(posedge clock);
   if (a == b)
       z <= x + y;
end
endmodule;

Verilog also supports the other comparison operators you'd normally expect (!=, <=, etc.). Synthesizers are fairly "smart", so something like x != 0 will normally synthesize to an N-input OR gate instead of a comparator.

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热鲨 2024-09-08 04:48:49

// this should work as comparator for Equality
wire [31:0] Cmp1, Cmp2;
wire Equal;
assign Equal  =  &{Cmp1 ~^ Cmp2}; // using XNOR
assign Equal  = ~|{Cmp1  ^ Cmp2}; // using XOR

// this should work as comparator for Equality
wire [31:0] Cmp1, Cmp2;
wire Equal;
assign Equal  =  &{Cmp1 ~^ Cmp2}; // using XNOR
assign Equal  = ~|{Cmp1  ^ Cmp2}; // using XOR

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