计算微控制器板载 ADC 的最大物理速率（奈奎斯特性能限制）
我正在尝试评估集成在各种 PIC 微控制器上的 A/D 的最大物理速率（奈奎斯特性能限制）。
然而，进行计算需要一些我在数据表中没有明确说明的参数，特别是 Tacq、Fosc、TAD 和除数参数。
我已经做了一些假设，但这有助于进行健全性检查——我是否正确地进行了最大物理速率计算？
仅出于说明目的，我采用了最简单的带有 ADC 的 PIC10F220。这是为了特别关注 Tacq、Fosc、TAD 和除数参数的解释，而不是建议可以在这个非常基本的芯片上实现任何实用功能。 （这是 Clifford 在下面评论中的观点。）
计算：
Nyquist Performance Analysis of PIC10F220
- Runs at clock speed of 8MHz.
- Has an instruction cycle of 0.5us [4 clock steps per instruction]
因此：
- Get Tacq = 6.06 us [acquisition time for ADC, assuming chip temp. = 50*C]
[from datasheet p34]
- Set Fosc := 8MHz [? should this be internal clock speed ?]
- Set divisor := 4 [? assuming this is 4 from 4 clock steps per CPU instruction ?]
- This gives TAD = 0.5us [TAD = 1/(Fosc/divisor) ]
- Get conversion time is 13*TAD [from datasheet p31]
- This gives conversion time 6.5 us
- So ADC duration is 12.56 us [? Tacq + 13*TAD]
假设在下一个示例之前实时完成 10 条简单加载/存储/阈值指令（这只是一个存根 - - 重点是计算的其余部分）：
- This adds another 5 us [0.5 us per instruction]
- To give total ADC and handling time of 17.56 us [ 12.56us + 1us + 4us ]
- before the sampling loop repeats [? Again Tacq ? + 13*TAD + handling ]
- If this is correct, then the max sampling rate is 56.9 ksps [ 1/ total time ]
- So the Nyquist frequency for this sampling rate is 28 kHz. [1/2 sampling rate]
这意味着该系统的（理论）性能（具有假设的实时处理代码的芯片 A/D）适用于带宽限制为 28 kHz 的信号。
在获取 Tacq、Fosc、TAD 和除数参数并使用它们来获取该芯片的最大物理速率或奈奎斯特性能限制时，这是对数据表的正确分配/解释吗？
谢谢，
I'm trying to evaluate the maximum physical rate (Nyquist performance limit) of the A/Ds integrated on board various PIC microcontrollers.
However, to do the calculation requires parameters that I'm not finding explicitly stated in the datasheets, specifically Tacq, Fosc, TAD, and divisor parameters.
I've proceeded by making some assumptions but would be helpful to have a sanity check -- am I doing the maximum physical rate calculations correctly?
For illustration purposes only, I've taken the simplest possible PIC10F220 that has an ADC. This is to focus specifically on the interpretation of Tacq, Fosc, TAD, and divisor parameters, and not to suggest that any practical functionality could be implemented on this very basic chip. (This is to Clifford's points in the comments below.)
Calculation:
Nyquist Performance Analysis of PIC10F220
- Runs at clock speed of 8MHz.
- Has an instruction cycle of 0.5us [4 clock steps per instruction]
So:
- Get Tacq = 6.06 us [acquisition time for ADC, assuming chip temp. = 50*C]
[from datasheet p34]
- Set Fosc := 8MHz [? should this be internal clock speed ?]
- Set divisor := 4 [? assuming this is 4 from 4 clock steps per CPU instruction ?]
- This gives TAD = 0.5us [TAD = 1/(Fosc/divisor) ]
- Get conversion time is 13*TAD [from datasheet p31]
- This gives conversion time 6.5 us
- So ADC duration is 12.56 us [? Tacq + 13*TAD]
Assuming 10 instructions for a simple load/store/threshold done in real-time before the next sample (this is just a stub -- the point is the rest of the calculation):
- This adds another 5 us [0.5 us per instruction]
- To give total ADC and handling time of 17.56 us [ 12.56us + 1us + 4us ]
- before the sampling loop repeats [? Again Tacq ? + 13*TAD + handling ]
- If this is correct, then the max sampling rate is 56.9 ksps [ 1/ total time ]
- So the Nyquist frequency for this sampling rate is 28 kHz. [1/2 sampling rate]
Which means the (theoretical) performance of this system --- chip's A/D with the hypothetical real-time handling code --- is for signals that are bandlimited to 28 kHz.
Is this a correct assignment / interpretation of the data sheet in obtaining Tacq, Fosc, TAD, and divisor parameters and using them to obtain the maximum physical rate, or Nyquist performance limit, of this chip?
Thanks,
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您无法用 8 条指令进行太多处理，但假设您只是做一些简单的事情，例如将传入的样本存储到缓冲区或检测阈值，那么您的分析看起来不错。
You're not going to be able to do much processing in 8 instructions, but assuming you're just doing something simple like storing the incoming samples to a buffer, or detecting a threshold, then your analysis looks good.
这是一个重要的区别； dsPIC ADC 同时支持多个通道的乒乓 DMA 传输，因此可以最大限度地减少每个样本的有效软件开销。这使得计算方式有所不同。您需要根据采样率和 DMA 缓冲区大小确定采样缓冲区中断之间的时间；这就是您必须处理每个缓冲区的处理时间。如果您使用 Microchip 的 DSP 库，它会为每种算法提供精确的周期时间公式，并且块处理比逐样本处理要高效得多。
我的上一个项目是在 dsPIC33 上进行的，具有两个以 48KHz 采样的通道和 32 字采样缓冲区（处理每对缓冲区需要 667us）。因此，软件处理完全独立于采样，因为通过使用 DMA，它们同时进行。
That is an important distinction; the dsPIC ADC supports ping-pong DMA transfers of multiple channels simultaneously, so can minimise the effective software overhead per sample. That makes the calculation a somewhat different one. You need to determine from the sample rate and the DMA buffer size the time between sample buffer interrupts; that is how much processing time you have to deal with each buffer. If you are using Microchip's DSP library, it gives precise cycle time formulae for each algorithm, and block processing is considerably more efficient that sample-by-sample processing.
My last project was on a dsPIC33 with two channels sampled at 48KHz and 32word sample buffers (giving 667us to process each pair of buffers). The software processing was therefore entirely independent of the sampling since by using DMA they take place simultaneously.