如何修复 vim 中自动缩进损坏的问题

发布于 2024-08-30 23:45:23 字数 1556 浏览 5 评论 0原文

我正在尝试使用 vim 7.2(在 Windows XP 上)自动缩进和格式化一些 VHDL 和 Matlab 代码。为此,我尝试使用“gg=G”命令。然而这不能正常工作。该代码根本没有正确缩进。

举个例子,我有以下源代码,它已经正确缩进了:

% This function is based on the code_g_generator() function
function [v_code] = get_code(n_code_number)
% There is no need to clear the persistent variables in this function
mlock 
%% Initialize the internal variables
persistent n_fifo_top;
if isempty(n_fifo_top)
    n_fifo_top = 1;
end

N_MEMORY_SIZE = 4;
if n_code_number > 4
    c_saved_code_fifo = {-1*ones(1, N_MEMORY_SIZE)};
end

如果我使用“gg=G”命令,我得到:

% This function is based on the code_g_generator() function
function [v_code] = get_code(n_code_number)
% There is no need to clear the persistent variables in this function
mlock 
%% Initialize the internal variables
persistent n_fifo_top;
if isempty(n_fifo_top)
        n_fifo_top = 1;
    end

    N_MEMORY_SIZE = 4;
    if n_code_number > 4
        c_saved_code_fifo = {-1*ones(1, N_MEMORY_SIZE)};
    end

正如你所看到的,在这个例子中,Vim 在第一个“if”之后错误地缩进了代码“ 堵塞。对于其他文件,我遇到类似的问题(尽管不一定在第一个 if 块上)。

对于 VHDL 文件,我遇到类似的问题。

我尝试过使用 autoindent、smartindent 和 cindent 设置的不同组合。在浏览这些论坛后,我还确保“语法”、“文件类型”、“文件类型缩进”和“文件类型插件缩进”设置为打开。尽管如此,它仍然不起作用。另外,如果我执行“设置语法?”我得到的 matlab 文件为“matlab”,vhdl 文件为“vhdl”,这是正确的。如果我“设置 indentexpr”?对于 matlab 文件,我得到“GetMatlabIndent(v:lnum)”;对于 vhdl 文件,我得到“GetVHDLindent()”。

通过在另一台计算机(之前从未安装过 VIM)上全新安装 VIM 来尝试隔离问题(并确保问题不是由我安装的 vim 插件之一引起的)。在那台计算机上,我遇到了同样的问题(这就是为什么我认为我不需要给你 .vimrc,但如果你需要它,我也可以将它上传到这里)。

有什么想法吗?

I am trying to use vim 7.2 (on Windows XP) to automatically indent and format some VHDL and Matlab code. To do so I am trying to use the "gg=G" command. However this does not work properly. The code is not properly indented at all.

To give you an example, I had the following source code, which was already properly indented:

% This function is based on the code_g_generator() function
function [v_code] = get_code(n_code_number)
% There is no need to clear the persistent variables in this function
mlock 
%% Initialize the internal variables
persistent n_fifo_top;
if isempty(n_fifo_top)
    n_fifo_top = 1;
end

N_MEMORY_SIZE = 4;
if n_code_number > 4
    c_saved_code_fifo = {-1*ones(1, N_MEMORY_SIZE)};
end

If I use the "gg=G" command I get:

% This function is based on the code_g_generator() function
function [v_code] = get_code(n_code_number)
% There is no need to clear the persistent variables in this function
mlock 
%% Initialize the internal variables
persistent n_fifo_top;
if isempty(n_fifo_top)
        n_fifo_top = 1;
    end

    N_MEMORY_SIZE = 4;
    if n_code_number > 4
        c_saved_code_fifo = {-1*ones(1, N_MEMORY_SIZE)};
    end

As you can see, in this example Vim incorrectly indents the code after the first "if" block. For other files I get similar problems (although not necessarily on the first if block).

For VHDL files I get similar problems.

I have tried using different combinations of the autoindent, smartindent and cindent settings. After going through these forums I have also made sure that the "syntax", "filetype", "filetype indent" and "filetype plugin indent" are set to on. Still, it does not work. Also, if I do "set syntax?" I get "matlab" for matlab files and "vhdl" for vhdl files which is correct. And if I do "set indentexpr?" I get "GetMatlabIndent(v:lnum)" for matlab files and "GetVHDLindent()" for vhdl files.

To try to isolate the problem (and ensure that it is not due to one of the vim plugins that I have installed) by doing a fresh install of VIM on a different computer (in which VIM had never been installed before). On that computer I get the same sort of problems (that is why I do not think that I need to give you the .vimrc, but if you need it I can upload it here too).

Any ideas?

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攒眉千度 2024-09-06 23:45:23

请参阅 wiki 页面,了解 vim 中自动缩进的不同方法的说明。

页面上,您可以找到缩进文件对于 matlab,您可以将其与基于文件类型的缩进一起使用。 这里是一个类似的 VHDL。

See this wiki page for explanations of the different methods for automatic indentation in vim.

On this page you can find an indent file for matlab which you can use with filetype based indenting. Here is a similar one for VHDL.

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