更改目标体内的 Makefile 变量值
有没有办法在目标体内重新分配 Makefile 变量值?
我想做的是为调试编译添加一些额外的标志:
%.erl: %.beam
$(ERLC) $(ERLFLAGS) -o ebin $<
test: clean debug_compile_flag compile compile_test
debug_compile:
$(ERLCFLAGS) += -DTEST
因此,如果我调用 test 目标,我想清理我的环境,添加一些新标志(例如 -DTEST< /em> 到现有的),再次编译整个代码(首先是源代码,然后是测试模块)。
我不想复制/粘贴用于使用一些新标志集进行编译的代码,因为到处都有很多逻辑。
有没有一些简单的方法来重新定义变量值,以便我可以重用现有代码?
Is there a way to reassign Makefile variable value inside of the target body?
What I am trying to do is to add some extra flags for debug compilation:
%.erl: %.beam
$(ERLC) $(ERLFLAGS) -o ebin lt;
test: clean debug_compile_flag compile compile_test
debug_compile:
$(ERLCFLAGS) += -DTEST
So if I invoke test target I would like to clean up my environment, add some new flags (like -DTEST to the existing ones), compile the whole code once again (first sources, then test modules).
I do not want to copy/paste the code for compiling with some new flags set since there is a lot of logic put here and there.
Is there some easy way to redefine the variable value so I can reuse the existing code?
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是的,有一种简单的方法可以做到这一点,并且无需重新运行 Make。使用特定于目标的变量值:
Yes, there is an easy way to do it, and without rerunning Make. Use a target-specific variable value:
另一个答案在这里:在规则执行时定义 make 变量。
对于懒惰的人,您可以使用如下规则(
FLAG
和DEBUG
是我的变量):Another answer is here: Define make variable at rule execution time.
For the lazy, you can have rules like the following (
FLAG
andDEBUG
are my variables):这是我使用的解决方案:
如果运行
make main
则输出为:您可以看到原始值
"abc123"
在sub< /code> 并且新值
"qwerty"
在main
级别可见。Here is the solution I use:
If you run
make main
then the output is:You can see that the original value
"abc123"
is overwritten in thesub
and the new value"qwerty"
is visible at themain
level.要在命令行上覆盖,请尝试以下操作:
这不会更改 Makefile,但会更改变量。
To override on the command line try something like:
This won't change Makefile, but will alter the variable.
我想在 makefile 中添加一个目标来运行测试,这意味着使用一些调试标志重新编译源代码。伊恩的回答: https://stackoverflow.com/a/15561911/ 是唯一有效的解决方案。
这是我想出的 Makefile,它保证运行
make test
时的执行顺序:I wanted to add a target in a makefile to run tests, which implied recompiling the source code with some debug flags. Ian's answer: https://stackoverflow.com/a/15561911/ was the only solution that worked.
Here's the Makefile I came up with, which guaranties the order of execution when running
make tests
:编辑:正如Beta在其他答案中所解释的那样,这是可能的。
不可以。在 Makefile 中没有办法做到这一点。不过,您可以在
make
命令行上更改变量的值。如果您按如下方式重写 Makefile:然后,您可以使用以下命令调用 make 来执行测试:
Edit: As explained by Beta in the other answer, it is possible.
No. There is no way to do this in the Makefile. You can however change the value of a variable on the
make
command line. If you rewrite your Makefile as follows:Then, you can invoke make to perform your tests using: