其中在 Fetch-Execute 周期中是通过地址模式解码的值
我目前正在构建一个小型 CPU 解释器，它支持多种寻址模式，包括寄存器延迟和位移。它利用经典的 IF-ID-EX-MEM-WB RISC 管道。地址模式操作数的值在管道的哪个阶段被解码。例如：
addw r9, (r2), 8(r3)
(r2) 和 8(r3) 在哪个阶段会被解码为它们的实际值？
I'm currently building a small CPU interpreter that has support several addressing modes, including register-deferred and displacement. It utilizes the classic IF-ID-EX-MEM-WB RISC-pipeline. In what stage of the pipeline is the value for an address-moded operand decoded. For example:
addw r9, (r2), 8(r3)
In what stage is (r2) and 8(r3) would be decoded into their actual values?
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这是一个有趣的问题。
RISC 架构的一项特性是寄存器-寄存器操作。也就是说，计算指令（例如 ADD）的所有操作数必须已经位于寄存器中。这使得 RISC 实现能够享受常规管道，例如您在问题中提到的 IF-ID-EX-MEM-WB 管道。此约束还简化了内存访问和异常。例如，如果从存储器读取数据的唯一指令是加载指令，并且如果这些指令只有寄存器+位移这样的简单寻址模式，则给定指令最多可以引发一个存储器保护异常。
相比之下，CISC 架构通常允许丰富的操作数寻址模式，例如寄存器间接寻址和索引，如您的问题所示。这些架构的实现通常具有不规则的管道，由于在操作数可用于计算（ADD 等）之前发生一个或多个内存访问，管道可能会停止。
尽管如此，微架构师已经成功地实现了 CISC 架构的流水线化。例如，Intel 486 有一个管道，可以将操作数和结果读/写到内存中。因此，在实现 ADD [eax],42 时，有一个管道阶段从 8 KB d-cache 读取 [eax]，一个管道阶段执行加法，还有另一个管道阶段将总和写回到 [eax] 。
由于 CISC 指令和操作数的使用动态地非常混合且不规则，因此您的管道设计要么必须相当长才能考虑到最坏的情况，例如多次内存读取以访问操作数和内存写入以写回结果，或者它必要时必须停止管道以插入额外的内存访问。
因此，为了适应这些 CISCy 寻址模式，您可能需要 IF-ID-EA-RD1-RD2-EX-WR 管道（EA=eff addr、RD1=读操作 1、RD2=读操作 2、WR=将结果写入 RAM或 reg 文件）。
快乐黑客。
It's a funny question.
One property of RISC architectures is register-register operation. That is, all operands for computation instructions such as ADD must already be in registers. This enables RISC implementations to enjoy a regular pipeline such as the IF-ID-EX-MEM-WB pipeline you mention in your question. This constraint also simplifies memory accesses and exceptions. For example, if the only instructions to read data from memory are load instructions, and if these instructions have only a simple addressing mode like register+displacement, then a given instruction can incur at most one memory protection exception.
In contrast, CISC architectures typically permit rich operand addressing modes, such as register indirect, and indexed as in your question. Implementations of these architectures often have an irregular pipeline, which may stall as one or more memory accesses are incurred before the operands are available for the computation (ADD etc.).
Nonetheless, microarchitects have successfully pipelined CISC architectures. For example, the Intel 486 had a pipeline that enabled operands and results to be read/written to memory. So when implementing ADD [eax],42, there was a pipeline stage to read [eax] from the 8 KB d-cache, a pipeline stage to perform the add, and another pipeline stage to write-back the sum to [eax].
Since CISC instruction and operand usage is dynamically quite mixed and irregular, your pipeline design would either have to be rather long to account for the worst case, e.g. multiple memory reads to access operands and a memory write to write-back a result, or it would have to stall the pipeline to insert the additional memory accesses when necessary.
So to accomodate these CISCy addressng modes, you might need a IF-ID-EA-RD1-RD2-EX-WR pipeline (EA=eff addr, RD1=read op 1, RD2=read op 2, WR=write result to RAM or reg file).
Happy hacking.
正如 Jan Gray 指出的，您提到的 CISC 指令
addw r9, (r2), 8(r3)不直接映射到 IF-ID-EX-MEM-WB RISC 管道。
但是，您也可以考虑将 CISC 指令分解为类似RISC的微指令
通过这种uop（微操作）分解，
地址计算 (r2) 和 8(r3) 将在各自的 EX 管道级中完成，
以及 MEM 管道级中及其周围的实际内存访问。
正如 Jan 提到的，i486 有一个不同的管道，即所谓的加载操作管道：
IF-ID-AGU-MEM-EX-WB，其中 AGU 是地址生成单元/管道级。
不同的 uop 分解。
这允许使用在 AGU 管道级中完成的地址计算 (r2) 和 8(r3) 进行
As Jan Gray pointed out, the CISC instruction you mention
addw r9, (r2), 8(r3)does not map directly onto a IF-ID-EX-MEM-WB RISC pipeline.
But rather than creating a IF-ID-EA-RD1-RD2-EX-WR pipeline (which I don't think works for ths case anyway, at least not in my notation), you might also consider breaking the CISC instruction up into RISC-like microinstructions
With this uop (micro-operation) decomposition,
the address computations (r2) and 8(r3) would be done in their respective EX pipestages,
and the actual memory access in and around the MEM pipestage.
As Jan mentions, the i486 had a different pipeline, a so-called load-op pipeline:
IF-ID-AGU-MEM-EX-WB, where AGU is the address generation unit / pipestage.
This permits a different uop decomposition
with the address computations (r2) and 8(r3) done in the AGU pipestage.
正如 Jan Gray 上面提到的，您尝试执行的指令实际上并不适用于该管道。您需要在 MEM 阶段加载数据，并在 EX 阶段（在 mem 之前）对其进行一些数学运算。
不过，要回答另一个相关问题，如果您想做的话：
“值修改操作数的值”的值是在 EX 阶段计算的。
As Jan Gray mentioned above, the instruction you are trying to execute doesn't really work for this pipeline. You need to load the data in the MEM stage, and do some math on it in the EX stage (which is before mem).
To answer another related question though, if you wanted to do:
The value for the 'value for the value-modded operand' is calculated in the EX stage.