综合 Verilog 代码时如何消除敏感列表警告？
我收到警告：
一个或多个信号丢失 始终阻止的敏感度列表。
always@(Address)begin
ReadData = instructMem[Address];
end
我该如何摆脱这个警告？
I am getting the warning that:
One or more signals are missing in the
sensitivity list of always block.
always@(Address)begin
ReadData = instructMem[Address];
end
How do I get rid of this warning?
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Verilog 不需要敏感列表中的信号名称。使用
@*语法表示只要always块的任何输入信号发生变化，就应触发该块：Verilog does not require signal names in the sensitivity list. Use the
@*syntax to signify that thealwaysblock should be triggered whenever any of its input signals change:将 InstructMem 添加到敏感度列表中。
Add InstructMem to the sensitivity list.
将 ReadData 声明为连线而不是 reg，然后用分配替换always块。
Declare
ReadDataas a wire instead of a reg and then replace your always block with an assign.我不确定 instructMem 的声明是什么样的。无论如何，使用典型的综合工具，ReadData = instructMem[address] 将导致多路复用器的地址被视为选择逻辑，而 instructMem 被视为多路复用器的数据线。您需要将 instructMem 放入敏感度列表中，因为每当这种情况发生变化时，ReadData 也应该发生变化。
我尝试了 Icarus，无论如何你都不能做类似总是 @(instructMem 或地址) 的事情，其中 instructMem 有一个像 reg [7:0] instructMem [255:0] --> 的声明。暗示着记忆。
注意：不要尝试以这种方式合成 Verilog 存储器，通常您应该实例化存储器 IP 并连接到它们的端口。供应商为此目的提供了内存模型。
I am not sure what the declaration of instructMem looks like. Anyway, ReadData = instructMem[address] is going to result in a multiplexer with address being treated as selection logic and instructMem as data lines of the multiplexer using a typical synthesis tool. You would need to put in instructMem in the sensitivity list since whenever this changes so should ReadData.
I tried Icarus, and you anyway cannot do something like always @(instructMem or address) where instructMem has a declaration like reg [7:0] instructMem [255:0] --> implying memory.
Note: do not try to synthesize Verilog memories this way, typically you are supposed to instantiate memory IPs and connect to their ports. Vendors provide memory models for such purposes.