ARM7处理器何时增加其PC寄存器？
我想了一会儿这个问题：ARM7（有3条管线）处理器什么时候增加它的PC寄存器。
我原本以为一条指令执行完后，处理器首先检查上一次执行是否有异常，然后根据当前状态将PC加2或4。如果发生异常，ARM7将改变其运行模式，将PC存储在当前模式的LR中，并开始处理当前异常，而不修改PC寄存器。
但在分析返回指令时没有任何意义。我不明白为什么当从未定义指令异常返回时 PC 会被分配 LR，而从预取中止异常返回时会被分配 LR-4，这两个异常不是都发生在解码状态吗？更重要的是，根据我的教科书，当从预取中止异常返回时，无论处理器在异常发生之前处于什么状态（ARM或Thumb），PC总是会被分配LR-4。然而，我认为如果原始状态是 Thumb，PC 应该被分配 LR-2，因为 Thumb 指令是 2 个字节长，而不是 ARM 指令保存的 4 个字节长，而且我们只想回滚当前状态下的指令。是我的推理有问题还是课本有问题。
似乎是一个很长的问题。我真的希望任何人都可以帮助我得到正确的答案。
提前致谢。
I'm thinking about this question for a time: when does an ARM7(with 3 pipelines) processor increase its PC register.
I originally thought that after an instruction has been executed, the processor first check is there any exception in the last execution, then increase PC by 2 or 4 depending on current state. If an exception occur, ARM7 will change its running mode, store PC in the LR of current mode and begin to process current exception without modifying the PC register.
But it make no sense when analyzing returning instructions. I can not work out why PC will be assigned LR when returning from an undefined-instruction-exception while LR-4 from prefetch-abort-exception, don't both of these exceptions happened at the decoding state? What's more, according to my textbook, PC will always be assigned LR-4 when returning from prefetch-abort-exception no matter what state the processor is(ARM or Thumb) before exception occurs. However, I think PC should be assigned LR-2 if the original state is Thumb, since a Thumb-instruction is 2 bytes long instead of 4 bytes which an ARM-instruction holds, and we just wanna roll-back an instruction in current state. Is there any flaws in my reasoning or something wrong with the textbook.
Seems a long question. I really hope anyone can help me get the right answer.
Thanks in advance.
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您从未定义指令处理返回到 LR，因为它指向导致陷阱的指令之后的指令；你不想再次返回相同的未定义指令，它只会遇到相同的陷阱。
如果你想再次执行相同的指令，你可以从预取中止返回到 LR-4；大概是因为您已经为其映射了一些内存，所以它现在可以工作了。
ARM7 在管道中的哪个点实际上增加其 PC 是无关紧要的，因为执行期间 PC 的值以及因此中止处理程序中 LR 的值是作为 ARM 架构标准的一部分规定的内容，主要基于古代 ARM2 在 PC 上所做的事情。
这才有意义，但是异常处理程序需要知道导致其触发的原始代码是 ARM 还是 Thumb 代码。这也可能会影响兼容性，因为周围有大量非 Thumb 感知的异常处理代码。因此，Thumb 架构在异常处理程序的入口处伪造了 LR，以便处理程序始终可以使用相同的指令来返回，即它们习惯于用于非 Thumb 代码的指令。
You return to LR from undefined-instruction handling because that points to the instruction after the one that caused the trap; you don't want to return to the same undefined instruction again, it'll only hit the same trap.
You return to LR-4 from prefetch-abort if you want to execute the same instruction again; presumably because you've mapped some memory in for it so it'll now work.
At what point in the pipeline an ARM7 actually increases its PC is irrelevant, because the value of PC during execution and consequently the value of LR in abort handlers is something laid down as part of the ARM architecture standard, based largely on what the ancient ARM2 did with its PC.
That would make sense, but then the exception handler would need to know whether the original code that caused it to trigger was ARM or Thumb code. This might have impacted compatibility too, as there was plenty of non-Thumb-aware exception handling code around. So instead the Thumb architecture fudged the LR on entry to exception handlers so that the handler could always use the same instruction to return, the one they were used to using for non-Thumb code.