在单周期数据路径中加载半字和加载字节
有人询问如何在单周期数据路径中实现加载字节而无需更改数据存储器，解决方案如下。
替代文本 http://img214.imageshack.us/img214/7107/99897101.jpg
这其实是很现实的 问题;大多数记忆系统是 完全基于单词和个人 字节通常只被处理 处理器内部。当你看到一个 许多计算机上出现“总线错误”，这 通常意味着处理器尝试过 访问一个内存地址 字对齐不正确，并且 内存系统引发异常。 无论如何，因为字节地址可能 不是 4 的倍数，我们不能通过 直接将它们存储到内存中。然而，我们 仍然可以获得任何字节，因为 每个字节都可以在某些内找到 字，所有字地址都是 4的倍数。所以我们首先要做的就是 要做的就是确保我们得到正确的 单词。如果我们取高 30 位 地址（即 ALUresult[31-2]） 并将它们与两个 0 位组合在一起 低端（这就是“左 班次 2” 单位确实在做），我们 具有该字的字节地址 包含所需的字节。这是 只是字节自己的地址，四舍五入 减少到 4 的倍数。这个变化 意味着 lw 现在也将舍入 地址低至 4 的倍数，但是 没关系，因为地址不对齐 无论如何，这对 lw 不起作用 记忆单元。好的，现在我们得到数据了 从记忆中回想起这个词。我们如何得到 我们想要从中得到什么字节？出色地， 请注意该字节的字节偏移量 在这个词中只是给出了 字节的低 2 位 地址。所以，我们只需使用这 2 个 位来选择适当的字节 使用多路复用器无法言表。请注意 使用大端字节编号，如 适用于 MIPS。接下来，我们 必须将字节零扩展为 32 位（即，只需将其与 24 零在其高端），因为 问题指定这样做。实际上， 这是一个小错误 问题：实际上，lbu 指令对字节进行零扩展，但是 lb 符号扩展它。那好吧。 最后，我们必须延长 MemtoReg 控制的多路复用器接受一个 新输入：零扩展字节 磅案。 MemtoReg 控件 信号必须加宽至 2 位。这 原来的0和1情况改为00 和 01，我们添加一个新的 case 10 只在case中使用 磅。
也不太明白这是如何工作的，尤其是关于将 ALU 结果左移 2 将给出字节地址......这怎么可能？所以如果我想加载一个半字，那么我会做一次左移，然后我会得到半字的地址？通过修改数据存储器来加载字节、加载半字的更好方法是什么？ （上面的问题限制了我们不能修改数据内存）
There was this problem that has been asked about implementing a load byte into a single cycle datapath without having to change the data memory, and the solution was something below.
alt text http://img214.imageshack.us/img214/7107/99897101.jpg
This is actually quite a realistic
question; most memory systems are
entirely word-based, and individual
bytes are typically only dealt with
inside the processor. When you see a
“bus error” on many computers, this
often means that the processor tried
to access a memory address that was
not properly word-aligned, and the
memory system raised an exception.
Anyway, because byte addresses might
not be a multiple of 4, we cannot pass
them to memory directly. However, we
can still get at any byte, because
every byte can be found within some
word, and all word addresses are
multiples of 4. So the first thing we
do is to make sure we get the right
word. If we take the high 30 bits of
the address (i.e., ALUresult[31-2])
and combine them with two 0 bits at
the low end (this is what the “left
shift 2” unit is really doing), we
have the byte address of the word that
contains the desired byte. This is
just the byte’s own address, rounded
down to a multiple of 4. This change
means that lw will now also round
addresses down to multiples of 4, but
that’s OK since non-aligned addresses
wouldn’t work for lw anyway with this
memory unit. OK, now we get the data
word back from memory. How do we get
the byte we want out of it? Well,
note that the byte’s byte-offset
within the word is just given by the
low-order 2 bits of the byte’s
address. So, we simply use those 2
bits to select the appropriate byte
out of the word using a mux. Note the
use of big-endian byte numbering, as
is appropriate for MIPS. Next, we
have to zero-extend the byte to 32
bits (i.e., just combine it with 24
zeros at its high end), because the
problem specifies to do so. Actually,
this was a slight mistake in the
question: in reality, the lbu
instruction zero-extends the byte, but
lb sign-extends it. Oh, well.
Finally, we have to extend the
MemtoReg-controlled mux to accept one
new input: the zero-extended byte for
the lb case. The MemtoReg control
signal must be widened to 2 bits. The
original 0 and 1 cases change to 00
and 01, respectively, and we add a new
case 10 which is only used in the case
of lb.
I don't quite actually understand on how this works even after reading the explanation, especially about left shift the ALU result by 2 would give the byte address... how is this possible?? so if I would like to load a half word then I would do one left shift and I would get the address of the half word?? what would be a better way to do load byte, load half word by modifying the data memory? (the question above puts constraints that we can't modify the data memory)
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原作者似乎只是在从内存读取的 32 位数据中添加了一个字节多路复用器。该存储器允许完整的 32 位自然对齐加载（lw 指令），并且附加字节多路复用器和零扩展也允许加载字节指令（lbu 指令）。
ALU 结果的左移产生一个字地址，不是字节地址，并解释了信号路由中隐式右移两位的原因。最终结果只是 ALU 结果的低两位在发送到内存之前被屏蔽（清零）。 ALU 值的两个 LSB 被馈送到存储器下游的字节多路复用器，允许字存储器读取任意字节。
所示逻辑中没有直接支持加载半字（16 位），仅支持字节和完整 32 位字。但是，您可以使用类似的方法轻松修改字节寻址逻辑以支持字而不是字节（甚至两者）。
The original author simply seems to be adding a byte multiplexer to the 32-bit data being read from the memory. This memory allows a full 32-bit naturally aligned load (lw instruction) and the additional byte multiplexer and zero extension allows for load byte instructions as well (lbu instruction).
The left shift of the ALU result yields a word address, NOT a byte address, and accounts for the implicit right shift by two in the signal routing. The end result is simply the lower two bits of the ALU result being masked (zeroed) before being sent to the memory. The two LSBs of the ALU value are fed down-stream of the memory to the byte multiplexer, allowing the word memory to read arbitrary bytes.
There is no direct support in the logic shown for loading half-words (16-bits), just bytes and full 32-bit words. You could, however, easily modify the byte addressing logic to support words instead of bytes (or even both) using a similar approach.