x86/x64 芯片仍然使用微编程吗？
如果我理解这两篇文章，英特尔架构在最低级别上已经过渡到使用 RISC 指令，而不是英特尔闻名的传统 CISC 指令集：
http://www.hardwaresecrets.com/article/235/4
http://www.tomshardware.com/reviews/intel,264-6.html
如果是这样的话，那么就是 x86/x64 芯片仍然是微编程的还是像传统 RISC 芯片一样使用硬连线控制？我猜它仍然是微程序化的，但想验证一下。
If I understand these two articles, the Intel architecture, at it's lowest level, has transitioned to using RISC instructions, instead of the the traditional CISC instruction set that Intel is known for:
http://www.hardwaresecrets.com/article/235/4
http://www.tomshardware.com/reviews/intel,264-6.html
If that's the case, then are x86/x64 chips still microprogrammed or does it use hardwired control like traditional RISC chips? I'm going to guess it's still microprogrammed but wanted to verify.
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微代码已经存在很长时间了（如果这就是您所指的）。所以我不知道 HardwareSecrets 文章是关于什么的，除非英特尔现在正在 CISC 处理器之上构建 RISC 处理器。
甚至 HardwareSecrets 文章也将其称为微指令。马铃薯，马铃薯。
http://en.wikipedia.org/wiki/Microcode
Microcode has been around for a long time, if that's what you're referring to. So I don't know what the HardwareSecrets article is on about, unless Intel is now building RISC processors on top of CISC processors.
Even the HardwareSecrets article calls them Micro-Instructions. Potato, potahto.
http://en.wikipedia.org/wiki/Microcode
在现代 x86 处理器上，大多数指令在执行时无需微码 (*)，但一些复杂或不经常执行的指令确实使用微码。
(*) 不要与微操作混淆——在 x86 乱序处理器中，x86 指令通常被解码为一个或多个微操作，然后在乱序中排队等待执行（无微代码！） -订单执行管道。
还值得注意的是，现代 x86 处理器具有修补/更新微代码的功能，以便在现场修复勘误表。
On modern x86 processors, most instructions execute without microcode (*), but some complex or infrequently executed ones do use microcode.
(*) Not to be confused with micro-ops -- in x86 out-of-order processors, x86 instructions are typically decoded into one or more micro-ops which then are queued for execution (sans microcode!) in the out-of-order execution pipeline.
It is also interesting to note that modern x86 processors have a facility to patch/update microcode in order to fix errata in the field.
刚刚找到答案。参考 Andrew Tanenbaum 的“计算机系统组织”，第 54 页至第 59 页。
英特尔芯片是基于 CISC 的，所有基于 CISC 的芯片都有一个解释器（微代码）来将复杂的指令分解为小步骤。早期所有芯片都包含微程序。直到 1980 年 David Patterson 和 Carlo Sequin 提出 RISC 概念之前，还没有 CISC 术语。
RISC 代表精简指令集计算机。在当今时代，指令集的大小并不重要。在 RISC 设计中，重要的是指令的简单性，但“简化”这个名称却一直沿用至今。
RISC 设计的目的是快速发出越来越简单的指令。一条指令需要多长时间并不重要，重要的是每秒可以启动多少条指令。
此外，使用更快的 CPU ROM 相对于更慢的主内存 CISC 设计的优势，随着同样更快的主内存的出现而消失。
RISC 的性能绝对优于 CISC。那么为什么芯片制造商Intel没有转向RISC呢？有两个原因。首先，存在向后兼容性的问题，并且公司已经在英特尔系列软件上投资了数十亿美元。其次，英特尔可以设法在其 CISC 芯片中使用 RISC 的思想。从 486 开始，Intel CPU 包含一个 RISC 内核，它在单个数据路径周期中执行最简单和最常见的指令，同时以通常的 CISC 方式解释更复杂的指令。
我猜英特尔表面上转向了混合方法，以保持市场上的面子/声誉/商誉与技术进步保持一致。我认为英特尔芯片仅基于 CISC。
Just found the answer. Reference to "COMPUTER SYSTEMS ORGANIZATION" by Andrew Tanenbaum, page 54 to page 59.
Intel chips are CISC based and all CISC based chips have an interpreter (microcode) to break the complex instructions into small steps. Earlier all chips contained microprogram. there was no CISC term, till the time RISC concept was introduced by David Patterson and Carlo Sequin in 1980.
RISC stands for reduced instruction set computer. In today's time size of the instruction set does not matter. what matters in RISC design is simplicity of the instructions, but the name 'reduced'stuck.
RISC design is about issuing more and more simple instructions quickly. how long an instruction took mattered less than how many could be started per second.
Also the advantage of using faster CPU ROM over slower main memory CISC design had, is gone by the advent of equally faster main memory.
RISC is definitely better than CISC performance wise. then why chip maker Intel didn't move to RISC? for two reasons. first of all, there is the issue of backward compatibility and the billions of dollars companies have invested in software for intel line. secondly, intel could manage to use the idea of RISC in its CISC chips. starting from 486, intel CPUs contain a RISC core that executes the smiplest and most common instructions in a single data path cycle, while interpreting the more complicated instructions in the usual CISC way.
I guess Intel superficially moved on to the hybrid approach to keep the face/fame/goodwill in the market in line with the technology advances. I would take intel chips as CISC based only.
当前的 x86 CPU 仍然使用微代码，因为 x86 指令集相对于典型的 RISC 处理器非常复杂。至少对于某些指令来说是这样。
在内部，复杂的指令被分解为简单的类 RISC 指令，然后由复杂的类 RISC 内核进行处理。类 RISC 指令有时会重新排序或并行执行。
Current x86 CPUs still use microcode because the x86 instruction set is very complex relative to typical RISC processors. This is true at least for some instructions.
Internally, the complex instructions are broken into simple RISC-like instructions which are then processed by a sophisticated RISC-like core. The RISC-like instructions are sometimes re-ordered or executed in parallel.
微编码指令的典型示例是除法和乘法，CISC 和 RISC 都是这种情况。考虑到（相对）很少使用除法，在硬件中实现除法是不值得的。乘法的实现要简单得多，而且也是微编码的，尽管程度当然不同。根据此文档...x86 处理器的指令延迟和吞吐量 mul 的延迟K10 处理器的 div 是 5 和 77 或 15.4X。对于 intel SBR(?)，相应的值为 4 和 92 或 23X。关于它们相对复杂性的另一个见解是它们各自的吞吐量：在 K10 上，每隔一个时钟周期可以维持一次乘法（2.5 - 5/2 - 同时操作），但每 77 个时钟周期只能维持一次除法（与除法延迟相同） 。
其他示例包括 sh?d (shift ? double) 和 bs? （位扫描？）。
Typical examples of microcoded instructions are division and multiplication and this is the case for both CISC and RISC. It is just not worth it to implement division in hardware considering how (relatively) seldom it is used. Multiplications are much simpler to implement yet are also micro-coded though of course not to the same degree. According to this document Instruction Latencies and Throughput for ... x86 Processors the latencies for mul and div for the K10 processor is 5 and 77 or 15.4X. For intel SBR(?) the corresponding values are 4 and 92 or 23X. An additional insight as to their relative complexity is their respective throughput: on K10 a multiplication every other clock cycle can be sustained (2.5 - 5/2 - in operation simultaneously) but only sustain one division every 77th clock cycle (same as division latency).
Other examples are sh?d (shift ? double) and bs? (bit scan ?).