如何在 verilog 中不使用 while() 循环（用于综合）？

发布于 2024-08-23 06:04:12 字数 370 浏览 5 评论 0原文

我已经养成了开发大量测试平台并使用 for() 和 while() 循环进行测试的习惯。没关系。问题是我已经将这种习惯用于对应该可综合的电路进行编码。 XST 和其他人拒绝合成代码（无需对合成参数进行额外修改），例如：

while (num < test_number) 
     begin 
     . 
     . 
     . 
     num = num+1; 
     end

这是不好的编码风格，因为对于合成器 test_num 来说是一个值为 2^32 的 int！或者将其视为无界参数。不管怎样，这都是一种不好的编码习惯。但我已经习惯了在 C 和测试平台中这样做。上述代码段的等效可合成代码是什么？

谢谢！

原文

I've gotten in the habit of developing a lot testbenches and use for() and while() loops for testing purpose. Thats fine. The problem is that I've taken this habit over to coding for circuits which should be synthesizable. XST and others refuse to synthesize code (without additional modification to synthesis parameters) such as:

while (num < test_number) 
     begin 
     . 
     . 
     . 
     num = num+1; 
     end

This is bad coding style because to the synthesizer test_num is an int with value 2^32! or it sees it as unbounded parameter. Either way, its a bad coding habit. But I'm so used to doing this in C and testbenches. What would be the equivalent synthesizable of code of the above code segment?

Thanks!

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美煞众生 2024-08-30 06:04:12

综合工具各不相同，但通常只要综合工具已知迭代次数，就可以综合循环。所以，

for ( i = 0; i < 10; i = i + 1 )

没问题，因为该工具知道有 10 次循环迭代。但

reg [10:0] r;
for ( i = 0; i < r; i = i + 1 )

不行，因为 r 是一个变量，r 的值在合成时未知。

将 RTL 代码中的循环视为创建一段逻辑的已知固定数量的副本。

Synthesis tools vary but generally a loop can be synthesized so long as the number of iterations is known a to the synthesis tool. So,

for ( i = 0; i < 10; i = i + 1 )

is OK because the tool knows there are 10 loop iterations. But

reg [10:0] r;
for ( i = 0; i < r; i = i + 1 )

is not OK because r is a variable r's value is unknown at synthesis time.

Think of loops in RTL code as creating a known fixed number of copies of a piece of logic.

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绳情 2024-08-30 06:04:12

你需要有一个时钟来控制它启动。

always @(posedge clk or negedge rst_n)
  if (!rst_n)
     num <= 32'b0; // or whatever your width is.
  else
     if (num < test_number)
       num <= num + 1'b1;

You need to have a clock to control it to start.

always @(posedge clk or negedge rst_n)
  if (!rst_n)
     num <= 32'b0; // or whatever your width is.
  else
     if (num < test_number)
       num <= num + 1'b1;

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公布 2024-08-30 06:04:12

如果您的综合工具不支持 while 或 for 循环，则不要使用循环。只需扩展您的代码即可。

wire [1:0] addr;
reg  [3:0] wren;

always @(posedge clk) begin
    wren[0] <= (addr == 2'd0);
    wren[1] <= (addr == 2'd1);
    wren[2] <= (addr == 2'd2);
    wren[3] <= (addr == 2'd3);
end

我不熟悉 XST，但一些综合工具确实支持循环（例如 Synopsys）。

If your synthesis tool does not support while or for loops, then don't use a loop. Just expand your code out.

wire [1:0] addr;
reg  [3:0] wren;

always @(posedge clk) begin
    wren[0] <= (addr == 2'd0);
    wren[1] <= (addr == 2'd1);
    wren[2] <= (addr == 2'd2);
    wren[3] <= (addr == 2'd3);
end

I am unfamiliar with XST, but some synthesis tools do support loops (Synopsys, for example).

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