附加到 GNU ‘make’;通过命令行变量

发布于 2024-08-19 05:16:06 字数 461 浏览 8 评论 0原文

我正在使用 GNU Make Makefile 来构建具有多个目标的 C 项目(allclean 和一些项目特定目标)。在调试过程中,我想在单个构建中附加一些标志,而无需永久编辑 Makefile(例如,添加调试符号或设置预处理器标志)。

过去,我的做法如下(使用调试符号示例):

make target CFLAGS+=-g

不幸的是,这不是附加到 CFLAGS 变量,而是清除它并停止编译。有没有一种干净的方法可以做到这一点,而无需定义附加到 CFLAGS 和 LDFLAGS 末尾的某种虚拟变量?

I am using a GNU Make Makefile to build a C project with several targets (all, clean, and a few project specific targets). In the process of debugging, I would like to append some flags to a single build without permanently editing the Makefile (e.g., add debugging symbols or set a preprocessor flag).

In the past, I have done that as follows (using the debugging symbols example):

make target CFLAGS+=-g

Unfortunately, this is not appending to the CFLAGS variable, but instead, clearing it and stopping it from compiling. Is there a clean way of doing this without defining some sort of dummy variable appended to the end of CFLAGS and LDFLAGS?

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世态炎凉 2024-08-26 05:16:06

查看覆盖指令。您可能需要修改 makefile 一次,但它应该可以满足您的要求。

makefile 示例:

override CFLAGS += -Wall

app: main.c
    gcc $(CFLAGS) -o app main.c 

命令行示例:

$ make
gcc -Wall -o app main.c 
$ make CFLAGS=-g
gcc -g -Wall -o app main.c 

Check out the override directive. You will probably need to modify the makefile once, but it should do what you want.

Example makefile:

override CFLAGS += -Wall

app: main.c
    gcc $(CFLAGS) -o app main.c 

Example command lines:

$ make
gcc -Wall -o app main.c 
$ make CFLAGS=-g
gcc -g -Wall -o app main.c 
够钟 2024-08-26 05:16:06

作为记录,卡尔·诺勒姆的回答 <从命令行的角度来看,在变量前面添加。

我需要一种实际附加的方法并想出了:

override CFLAGS := -Wall $(CFLAGS)

For the record, Carl Norum's answer prepends the variable, from the command line perspective.

I needed a way to actually append and came up with:

override CFLAGS := -Wall $(CFLAGS)
梦中的蝴蝶 2024-08-26 05:16:06

有两种方法可以将变量传递给 make:

  • 使用命令行参数:

    使 VAR=值
    
  • 使用环境:

    导出 VAR=var;制作
    

    或者(更好,因为它只改变当前命令的环境)

    VAR=var make
    

它们略有不同。第一个更强。这意味着你知道自己想要什么。第二个可以被认为是一个提示。它们之间的区别在于运算符 =+= (没有 override)。在命令行中定义变量时,这些运算符将被忽略,但在环境中定义变量时,这些运算符不会被忽略。因此,我建议你有一个带有:的Makefile

CC ?= gcc
CFLAGS += -Wall
INTERNAL_VARS = value

并用以下方式调用它:

CFLAGS=-g make

注意,如果你想撤回-Wall,你可以使用:

make CFLAGS=

Please don't use override关键字,否则您将无法更改受override影响的变量。

There are two ways to pass variables to make:

  • Using command line arguments:

    make VAR=value
    
  • Using environment:

    export VAR=var; make
    

    or (better because it change environment only for current command)

    VAR=var make
    

They are slightly different. The first one is stronger. It mean you know what you want. The second may be considered like a hint. Difference between them is about operators = and += (without override). These operators are ignored when a variable is defined on command line, but are not ignored when variable is defined in environment. Thus, I suggest you to have a Makefile with:

CC ?= gcc
CFLAGS += -Wall
INTERNAL_VARS = value

and call it with:

CFLAGS=-g make

Notice, if you want to withdraw -Wall, you can use:

make CFLAGS=

Please don't use override keyword, else you won't have any way to change a variable affected with override.

琉璃梦幻 2024-08-26 05:16:06

请注意,因为我感到困惑 - 让它成为文件 testmake

$(eval $(info A: CFLAGS here is $(CFLAGS)))

override CFLAGS += -B

$(eval $(info B: CFLAGS here is $(CFLAGS)))

CFLAGS += -C

$(eval $(info C: CFLAGS here is $(CFLAGS)))

override CFLAGS += -D

$(eval $(info D: CFLAGS here is $(CFLAGS)))

CFLAGS += -E

$(eval $(info E: CFLAGS here is $(CFLAGS)))

然后:

$ make -f testmake
A: CFLAGS here is 
B: CFLAGS here is -B
C: CFLAGS here is -B
D: CFLAGS here is -B -D
E: CFLAGS here is -B -D
make: *** No targets.  Stop.
$ make -f testmake CFLAGS+=-g
A: CFLAGS here is -g
B: CFLAGS here is -g -B
C: CFLAGS here is -g -B
D: CFLAGS here is -g -B -D
E: CFLAGS here is -g -B -D
make: *** No targets.  Stop.

testmake 文件中删除 override 指令:

$ make -f testmake
A: CFLAGS here is 
B: CFLAGS here is -B
C: CFLAGS here is -B -C
D: CFLAGS here is -B -C -D
E: CFLAGS here is -B -C -D -E
make: *** No targets.  Stop.
$ make -f testmake CFLAGS+=-g
A: CFLAGS here is -g
B: CFLAGS here is -g
C: CFLAGS here is -g
D: CFLAGS here is -g
E: CFLAGS here is -g
make: *** No targets.  Stop.

所以,

  • 如果一个变量使用了override一次,它只能附加另一个带有override的语句(正常的赋值将被忽略);
  • 当根本没有覆盖时;尝试从命令行追加(如 +=)会覆盖该变量的每个实例。

Just a note, as I got confused - let this be file testmake:

$(eval $(info A: CFLAGS here is $(CFLAGS)))

override CFLAGS += -B

$(eval $(info B: CFLAGS here is $(CFLAGS)))

CFLAGS += -C

$(eval $(info C: CFLAGS here is $(CFLAGS)))

override CFLAGS += -D

$(eval $(info D: CFLAGS here is $(CFLAGS)))

CFLAGS += -E

$(eval $(info E: CFLAGS here is $(CFLAGS)))

Then:

$ make -f testmake
A: CFLAGS here is 
B: CFLAGS here is -B
C: CFLAGS here is -B
D: CFLAGS here is -B -D
E: CFLAGS here is -B -D
make: *** No targets.  Stop.
$ make -f testmake CFLAGS+=-g
A: CFLAGS here is -g
B: CFLAGS here is -g -B
C: CFLAGS here is -g -B
D: CFLAGS here is -g -B -D
E: CFLAGS here is -g -B -D
make: *** No targets.  Stop.

With the override directives deleted from the testmake file:

$ make -f testmake
A: CFLAGS here is 
B: CFLAGS here is -B
C: CFLAGS here is -B -C
D: CFLAGS here is -B -C -D
E: CFLAGS here is -B -C -D -E
make: *** No targets.  Stop.
$ make -f testmake CFLAGS+=-g
A: CFLAGS here is -g
B: CFLAGS here is -g
C: CFLAGS here is -g
D: CFLAGS here is -g
E: CFLAGS here is -g
make: *** No targets.  Stop.

So,

  • if a variable used override once, it can only be appended with another statement with override (the normal assignments will be ignored);
  • when there's been no override at all; trying to append (as in +=) from the command line overwrites every instance of that variable.
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