附加到 GNU ‘make’;通过命令行变量
我正在使用 GNU Make Makefile 来构建具有多个目标的 C 项目(all
、clean
和一些项目特定目标)。在调试过程中,我想在单个构建中附加一些标志,而无需永久编辑 Makefile(例如,添加调试符号或设置预处理器标志)。
过去,我的做法如下(使用调试符号示例):
make target CFLAGS+=-g
不幸的是,这不是附加到 CFLAGS 变量,而是清除它并停止编译。有没有一种干净的方法可以做到这一点,而无需定义附加到 CFLAGS 和 LDFLAGS 末尾的某种虚拟变量?
I am using a GNU Make Makefile to build a C project with several targets (all
, clean
, and a few project specific targets). In the process of debugging, I would like to append some flags to a single build without permanently editing the Makefile (e.g., add debugging symbols or set a preprocessor flag).
In the past, I have done that as follows (using the debugging symbols example):
make target CFLAGS+=-g
Unfortunately, this is not appending to the CFLAGS
variable, but instead, clearing it and stopping it from compiling. Is there a clean way of doing this without defining some sort of dummy variable appended to the end of CFLAGS
and LDFLAGS
?
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查看覆盖指令。您可能需要修改 makefile 一次,但它应该可以满足您的要求。
makefile 示例:
命令行示例:
Check out the override directive. You will probably need to modify the makefile once, but it should do what you want.
Example makefile:
Example command lines:
作为记录,卡尔·诺勒姆的回答 <从命令行的角度来看,在变量前面添加。
我需要一种实际附加的方法并想出了:
For the record, Carl Norum's answer prepends the variable, from the command line perspective.
I needed a way to actually append and came up with:
有两种方法可以将变量传递给 make:
使用命令行参数:
使用环境:
或者(更好,因为它只改变当前命令的环境)
它们略有不同。第一个更强。这意味着你知道自己想要什么。第二个可以被认为是一个提示。它们之间的区别在于运算符
=
和+=
(没有override
)。在命令行中定义变量时,这些运算符将被忽略,但在环境中定义变量时,这些运算符不会被忽略。因此,我建议你有一个带有:的Makefile并用以下方式调用它:
注意,如果你想撤回
-Wall
,你可以使用:Please don't use
override
关键字,否则您将无法更改受override
影响的变量。There are two ways to pass variables to make:
Using command line arguments:
Using environment:
or (better because it change environment only for current command)
They are slightly different. The first one is stronger. It mean you know what you want. The second may be considered like a hint. Difference between them is about operators
=
and+=
(withoutoverride
). These operators are ignored when a variable is defined on command line, but are not ignored when variable is defined in environment. Thus, I suggest you to have a Makefile with:and call it with:
Notice, if you want to withdraw
-Wall
, you can use:Please don't use
override
keyword, else you won't have any way to change a variable affected withoverride
.请注意,因为我感到困惑 - 让它成为文件
testmake
:然后:
从
testmake
文件中删除override
指令:所以,
override
一次,它只能附加另一个带有override
的语句(正常的赋值将被忽略);覆盖
时;尝试从命令行追加(如+=
)会覆盖该变量的每个实例。Just a note, as I got confused - let this be file
testmake
:Then:
With the
override
directives deleted from thetestmake
file:So,
override
once, it can only be appended with another statement withoverride
(the normal assignments will be ignored);override
at all; trying to append (as in+=
) from the command line overwrites every instance of that variable.