make - 从命令行指定要生成的目标名称
我正在查看 C makefile，我有一个问题。
我知道'make a'将生成目标a，它应该在makefile中定义。
我想知道目标名称本身是否可以作为 make 的参数提供。
即这就是我想要做的：
$(target_name) 是提供给命令“make”的名称。例如，“make foo”。
在 makefile 中，
$(目标名称) = 依赖项
命令
我不确定这是否可能...在 make 手册中也找不到任何内容。
如果有人能帮助我解决这个问题，那就太棒了。
谢谢，
I am looking at C makefile, and I have a question.
I know that 'make a' will make the target a, which is supposed to be defined in the makefile.
I want to know whether the target name itself can be supplied as an argument to make.
i.e. this is what I want to do:
$(target_name) is the name supplied to command 'make'. For example, 'make foo'.
and in the makefile,
$(target_name) = dependencies
command
I am not sure whether this is possible... could not find anything in the make manual too.
If anyone can help me with this, it'll be awesome.
Thanks,
如果你对这篇内容有疑问，欢迎到本站社区发帖提问 参与讨论，获取更多帮助，或者扫码二维码加入 Web 技术交流群。
绑定邮箱获取回复消息
由于您还没有绑定你的真实邮箱，如果其他用户或者作者回复了您的评论，将不能在第一时间通知您！
发布评论
评论（2）
您所询问的一切都是 make 默认情况下所做的事情 - 无需在 makefile 中编写任何特殊代码来执行此操作。您似乎对 make 相当困惑（例如，它与 C 没有特别相关）。最好的指南是 GNU Make 手册，它不仅仅是一本手册但是一个非常好的教程。
Everything you are asking about is what make does by default - there is no need to write any special code in the makefile to do this. You seem rather confused about make (it is not particularly C related, for example). The best guide to it is the GNU Make Manual, which is not only a manual but a pretty good tutorial.
我对 Makefile 有点陌生，但似乎您没有像那样在
Makefile中传递值。如果以下是您的Makefile您可以通过在终端中调用
make来传递参数I'm kind of new to Makefiles but it seems you don't pass values in
Makefilelike that. If the following is yourMakefileYou can pass parameters in by calling
makelike this in the terminal