构建 VHDL 克隆

发布于 2024-08-18 04:46:55 字数 64 浏览 2 评论 0原文

我计划为我的最后一年项目设计一种硬件模拟语言,例如 VHDL。我该怎么办呢?

任何帮助将不胜感激。

I am planning to design a hardware simulation language like VHDL for my final year project. How should I go about it ?

Any help would be greatly appreciated.

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评论(4

旧伤慢歌 2024-08-25 04:46:55

如果要设计硬件仿真语言,就从硬件开始。

确定您想要模拟硬件的级别 - 晶体管级别、开关级别、寄存器级别、行为级别以及其他级别。其他一切都从那里开始。一旦决定,您就会知道您的语言需要支持什么构造。

您需要知道您的语言可以使用哪种设备 - 晶体管、门、寄存器、多路复用器、内存、算术单元等等。然后,您需要为每个设备找到合适的型号。

最后,您肯定会想要限制您的范围。限制自己只做一件事。 VHDL 语言不是一个人一天发明的。

If you want to design a hardware simulation language, start with the hardware.

Determine the level at which you want to simulate the hardware - transistor level, switch level, register level, behavioural level and what nots. Everything else starts from there. Once that is decided, you will know what constructs your language needs to support.

You will need to know what kind of devices your language can work with - transistors, gates, registers, muxes, memory, arithmetic units and what nots. Then, you need to find the appropriate models for each device.

In the end, you will definitely want to limit your scope. Limit yourself to doing one thing. The VHDL language was not invented by a single person in a day.

习ぎ惯性依靠 2024-08-25 04:46:55

您是否收到过这个项目,或者您决定自己做这个项目?如果是后者,那么恐怕你可能需要重新考虑。遗憾的是,像这样的大型开放式项目并不总是会给学生带来好结果。

也就是说,如果您确实想这样做,那么您自己使用 VHDL 并阅读用户的评论。从中你会发现什么惹恼或激怒了用户,然后设计出更好的东西。

Have you been given this project or is one you have decided to do yourself ? If its the latter then you might want to rethink it I'm afraid. Big open ended projects like this don't always end well for the student sadly.

That said if you really want to do it then use VHDL yourself and read up on users comments on it. From that you will find out what annoys or irritates its users and then design something better.

童话 2024-08-25 04:46:55

如果您正在寻找更多并发语言的示例,可以考虑 MyHDL 和 XMOS XC,它们是传统 Verilog 和 VHDL 之外的其他尝试。

If you're looking for more examples of concurrent languages, there is MyHDL, and the XMOS XC which are other attempts away from the traditional Verilog and VHDL.

闻呓 2024-08-25 04:46:55

设计语言就像设计规范一样简单。您打算设计一个合成器和一个与之配套的模拟器吗?

Designing a language is as easy as designing a spec. Do you plan on designing a synthesizer and a simulator to go with it?

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